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onenand2g(kfg2g16q2m-debx) flash memory 1 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) * samsung electronics rese rves the right to change produc ts or specification without notice. information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about samsung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. onenand ? is a trademark of samsung electronics company, ltd. other names and brands may be claimed as the property of their rightful owners. kfg2g16q2m KFH4G16Q2M kfw8g16q2m 2gb onenand m-die
onenand2g(kfg2g16q2m-debx) flash memory 2 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) document title onenand revision history revision history revision no. 0.0 0.1 1.0 remark advanced preliminary final draft date mar. 30, 2006 aug., 3, 2006 sep. 20, 2006 history 1. initial issue. 1. corrected errata. 2. changed a tem from mat to plane. 3. chapter 1.4 & 2.3 & 8.0 : revised the package size from 11x13 to 10x13. 4. chapter 2.4 : revised avd pin description. 5. chapter 2.8.3 : eliminated top boot option. 6. chapter 2.8.12 & 2.8.16 & 3.8 : added a. comment about fsa & fcsa setting on cache read operation 7. chapter 2.8.18 : added acceptible command during busy on unlock, lock, lock-tight, all block unlock and erase suspend operation. 8. chapter 3.1 : eliminated read data from buffer and write data to buffer contents. 9. chapter 3.3.1& 4.2 & 6.18 : revised the bootcopy condtions. 10. chapter 3.3 : revised default value on start block address with hot reset. 11. chapter 3.5 : revised por level into 1.5v and resetting guidance. 12. chapter 3.11.1~3 : added details and restrictions about 2x program and 2x cache program. 13. chapter 3.11.3 & 6.16 : revised mandatory codition which is int auto mode for 2x interleave cache program into manually writable int cond- tion as 2x program or 2x cache program. 14. chapter 3.13.2 : eliminated the expression suspended on case 2. 15. chapter 3.14.1 : revised note 1 on otp load flow chart. 16. chapter 4.3 : revised load/program/erase current value and added "2x program current" item. 17. chapter 5.4 : revised tbdh(into 2ns on 83mhz) and tavdh(into 2ns on 66/83mhz). 18. chapter 5.8 : revised tavdh(into 2ns on 66/83mhz) 19. chapter 5.10 : revised twb table. 20. chapter 5.11 : revised tintl table and its value. 21. chapter 6.11 : added "start initial burst write operation" timing. 22. chapter 6.22 : revised timing diagram. 1. corrected errata. 2. chapter 3.1 : added restrictions of command based operation on ddp. 3. chapter 3.5 & 6.22 : corrected data protection explanation during power- down. 4. chapter 7.1 & 7.1.2 : added the case table of int type and comment regarding int pin connection when unused. 5. chapter 7.1.3 : corrected int behavior graphs.
onenand2g(kfg2g16q2m-debx) flash memory 3 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 1.0 introduction this specification contains information about the samsung electronics company onenand ? ? flash memory product family. section 1.0 includes a general overview, revision history, and product ordering information. section 2.0 describes the onenand device. section 3.0 provides information about device operation. electrical specifications an d timing waveforms are in sections 4.0 though 6.0. section 7.0 provides additional application and technical notes pertaining to use of the onenand. package dimensions are found in section 8.0 density part no. v cc (core & io) temperature pkg 2gb kfg2g16q2m-debx 1.8v(1.7v~1.95v) extended 63fbga(lf) 4gb KFH4G16Q2M-debx 1.8v(1.7v~1.95v) extended 63fbga(lf) 8gb kfw8g16q2m-debx 1.8v(1.7v~1.95v) extended 63fbga(lf) samsung offers a variety of flash solutions including nand flash, onenand ? and nor flash. samsung offers flash products both component and a variety of card formats including rs-mmc, mmc, compactflash, and smartmedia. to determine which samsung flash product solution is best for your application, refer the product selector chart. application requires samsung flash products nand onenand ? nor fast random read x fast sequential read xx fast write/program xx multi block erase x (max 64 blocks) x erase suspend/resume xx copyback x (edc) x (ecc) lock/unlock/lock-tight xx ecc external (hardware/software) internal x scalability xx 1.1 flash product type selector
onenand2g(kfg2g16q2m-debx) flash memory 4 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 1.2 ordering information k f x x 1 6 q 2 m - d e x x samsung onenand memory device type g : single chip h : dual chip w: quad chip density 2g : 2gb 4g : 4gb 8g : 8gb operating temperature range e = extended temp. (-30 q c to 85 q c) page architecture 2 : 2kb page version 1st generation product line desinator b : include bad block d : daisy sample operating voltage range q : 1.8v(1.7 v to 1.95v) package d : fbga(lead free) organization x16 organization speed 6 : 66mhz 8 : 83mhz onenand is a highly integrated non-volatile memory solution based around a nand flash memory array. the chip integrates system features including: x a bootram and bootloader x two independent bi-directional 2kb dataram buffers x a high-speed x16 host interface x on-chip error correction x on-chip nor interface controller this on-chip integration enables system designers to reduce external system logic and use high-density nand flash in applicatio ns that would otherwise have to use more nor components. onenand takes advantage of the higher performance nand program time, low power, and high density and combines it with the synchronous read performance of nor. the nor flash host interface makes onenand an ideal solution for applications like g3 smart phones, camera phones, and mobile applications that have large, advanced multimedia applications and operating systems, but lack a nand controller. when integrated into a samsung multi-chip-package with samsung mobile ddr sdram, designers can complete a high-perfor- mance, small footprint solution. 1.3 architectural benefits
onenand2g(kfg2g16q2m-debx) flash memory 5 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 1.4 product features device architecture x design technology: x supply voltage: x host interface: x 5kb internal bufferram: x slc nand array: device performance x host interface type: x programmable burst read latency: x multiple sector read/write: x multiple reset modes: x multi block erase: x low power dissipation: x reliable cmos floating-gate technology system hardware x voltage detector generating internal reset signal from vcc x hardware reset input (rp ) x data protection modes x user-controlled one time programmable(otp) area x internal 2bit edc / 1bit ecc x internal bootloader supports booting solution in system x handshaking feature x detailed chip information packaging x 2g products x 4g ddp products x 8g qdp products m die 1.8v (1.7v ~ 1.95v) 16 bit 1kb bootram, 4kb dataram (2k+64)b page size, (128k+4k)b block size synchronous burst read - up to 66mhz / 83mhz clock frequency - linear burst 4-, 8-, 16-, 32-words with wrap around - continuous 1k words sequential burst synchronous burst block read - up to 66mhz / 83mhz clock frequency - linear burst 4-, 8-, 16-, 32-, 1k-words with no-wrap - continuous (1k words) 64 page sequential burst synchronous write - up to 66mhz / 83mhz clock frequency - linear burst 4-, 8-, 16-, 32-, 1k-words with wrap around - continuous 1k words sequential burst asynchronous random read - 76ns access time asynchronous random write latency 3,4(default),5,6 and 7. 1~40mhz : latency 3 available 1~66mhz : latency 4,5,6 and 7 available over 66mhz : latency 6,7 available. up to 4 sectors using sector count register cold/warm/hot/nand flash core reset up to 64 blocks typical power, - standby current : 10ua (single) - synchronous burst read current(66mhz/83mhz, single) : 20/25ma - synchronous burst write current(66mhz/83mhz, single) : 20/25ma - load current : 30ma - program current : 25ma - erase current : 20ma - multi block erase current : 20ma - endurance : 100k program/erase cycles - data retention : 10 years - write protection for bootram - write protection for nand flash array - write protection during power-up - write protection during power-down - 1st block otp - int pin indicates ready / busy - polling the interrupt register status bit - by id register 63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch fbga 63ball, 10mm x 13mm x max 1.2mmt , 0.8mm ball pitch fbga 63ball, 10mm x 13mm x max 1.4mmt , 0.8mm ball pitch fbga
onenand2g(kfg2g16q2m-debx) flash memory 6 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) onenand ? ? is a monolithic integrated circuit with a nand flash array using a nor flash interface. this device includes control logic, a nand flash array, and 5kb of internal bufferram. the bufferram reserves 1kb for boot code buffering (bootram) and 4kb for data buffering (dataram), split between 2 independent buffers. it has a x16 host interface and a random access time speed o f ~76ns. the device operates up to a maximum host-driven clock f requency of 66mhz / 83mhz for synchronous reads at vcc(or vccq. refer to chapter 4.2) with minimum 6-clock latency. below 40mhz it is accessible with minimum 3-clock latency. appropriate wait cycl es are determined by programmable read latency. onenand provides for multiple sector read operations by assigning the number of sectors to be read in the sector counter register. the device includes one block-sized otp (one time programmable) ar ea and user-controlled 1st block otp(block 0) that can be used to increase system security or to provide identification capabilities. 1.5 general overview the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you h ave any questions, please contact the samsung branch office near you.
onenand2g(kfg2g16q2m-debx) flash memory 7 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 2.1 detailed product description the onenand is an advanced generation, high-performance nand-based flash memory. it integrates on-chip a single-level-cell (slc) nand flash array memory with two independent data buffers, boot ram buffer, a p age buffer for the flash array, and a one-time-programmable block. the combination of these memory areas enable high-speed pipelining of reads from host bufferram page buffer and nand flash array. clock speeds up to 66mhz / 83mhz with a x16 wide i/o yields a 108mbyte/second bandwidth. the onenand also includes a boot ram and boot loader. this enables the device to efficiently load boot code at device startup f rom the nand array without the need for off-chip boot device. one block of the nand array is set aside as an otp memory area, and 1st block (block 0) can be used as otp area. this area, available to the user, can be configured and locked with secured user information. on-chip controller interfaces enable the device to operate in systems without nand host controllers. 2.0 device description
onenand2g(kfg2g16q2m-debx) flash memory 8 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) b (capital letter) byte, 8bits w (capital letter) word, 16bits b (lower-case letter) bit ecc error correction code calculated ecc ecc that has been calculated during a load or program access written ecc ecc that has been stored as data in the nand flash array or in the bufferram bufferram on-chip internal buffer consisting of bootram and dataram bootram a 1kb portion of the bufferram reserved for boot code buffering dataram a 4kb portion of the bufferram reserved for data buffering sector part of a page of which 512b is the main data area and 16b is the spare data area. it is also the minimum load/program/copy-back program unit during a 1~4 sector operation is available. data unit possible data unit to be read from memory to bufferram or to be programmed to memory. - 528b of which 512b is in main area and 16b in spare area - 1056b of which 1024b is in main area and 32b in spare area - 1584b of which 1536b is in main area and 48b in spare area - 2112b of which 2048b is in main area and 64b in spare area 2.2 definitions
onenand2g(kfg2g16q2m-debx) flash memory 9 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 2.3.1 2gb product (kfg2g16q2m) 2.3 pin configuration nc nc nc nc int a0 a1 nc a10 a6 nc nc nc we rp dq14 v ss v ss dq13 dq12 dq8 dq1 oe dq9 v cc dq7 dq4 dq11 dq10 dq3 v cc dq15 a12 dq0 dq5 dq6 ce dq2 nc nc a9 avd a7 a11 a8 a4 a5 a2 a3 nc nc nc nc nc nc nc nc nc core io clk a15 a13 a14 rdy (top view, balls facing down) 63ball fbga onenand chip 63ball, 10mm x 13mm x max 1.0mmt , 0.8mm ball pitch fbga
onenand2g(kfg2g16q2m-debx) flash memory 10 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) nc nc nc nc int a0 a1 nc a10 a6 nc nc nc we rp dq14 v ss v ss dq13 dq12 dq8 dq1 oe dq9 v cc dq7 dq4 dq11 dq10 dq3 v cc dq15 a12 dq0 dq5 dq6 ce dq2 nc nc a9 avd a7 a11 a8 a4 a5 a2 a3 nc nc nc nc nc nc nc nc nc core io clk a15 a13 a14 rdy (top view, balls facing down) 63ball fbga onenand chip 63ball, 10mm x 13mm x max 1.2mmt , 0.8mm ball pitch fbga 2.3.2 4gb product (KFH4G16Q2M)
onenand2g(kfg2g16q2m-debx) flash memory 11 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) nc nc nc nc int1 a0 a1 nc a10 a6 nc nc nc we rp dq14 v ss v ss dq13 dq12 dq8 dq1 oe dq9 v cc dq7 dq4 dq11 dq10 dq3 v cc dq15 a12 dq0 dq5 dq6 ce1 dq2 int2 nc a9 avd a7 a11 a8 a4 a5 a2 a3 ce2 nc nc nc nc nc nc nc nc core io clk a15 a13 a14 rdy (top view, balls facing down) 63ball fbga onenand chip 63ball, 10mm x 13mm x max 1.4mmt , 0.8mm ball pitch fbga 2.3.3 8gb product (kfw8g16q2m)
onenand2g(kfg2g16q2m-debx) flash memory 12 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) note: do not leave power supply(vcc-core/vcc-io, v ss ) disconnected. pin name type nameand description host interface a15~a0 i address inputs - inputs for addresses during read and write operation, which are for addressing bufferram & register. dq15~dq0 i/o data inputs/outputs - inputs data during program and commands for all operations, outputs data during memory array/ register read cycles. data pins float to high-impedance when the chip is deselected or outputs are disabled. int / int1 o interrupt notifies the host when a command is completed. after power-up, it is at hi-z condition. once iobe is set to 1, it does not float to hi-z condition even when ce is disabled or oe is disabled. especially, in case of ddp, when reset(cold, warm, hot, nand flash core) command and 2x program command(007dh) are issued, it operates as open drain output with internal resistor (~50kohm). the int is the interrupt for single or ddp device. the int1 is the interrupt for the first ddp device(KFH4G16Q2M) in qdp(kfw8g16q2m) int2 o interrupt the int2 is the interrupt for the second ddp device(KFH4G16Q2M) in qdp(kfw8g16q2m) rdy o ready indicates data valid in synchronous read modes and is activated while ce is low clk i clock clk synchronizes the device to the system bus frequency in synchronous read mode. the first rising edge of clk in conjunction with avd low latches address input. we i write enable we controls writes to the bufferram and registers. datas are latched on the we pulses rising edge avd i address valid detect iindicates valid address presence on address inputs. during asynchronous read operation, all addresses are valid while avd is low, and during synchronous read operation, all addresses are latched on clks rising edge while avd is held low for one clock cycle. > low : for asynchronous mode, indicates valid address; for burst mode, causes starting address to be latched on rising edge on clk > high : device ignores address inputs rp i reset pin when low, rp resets internal operation of onenand. rp status is dont care during power-up and bootloading. when high, rp level must be equivalent to vcc-io / vccq level. ce / ce1 i chip enable ce -low activates internal control logic, and ce -high deselects the device, places it in standby state, and places dq in hi-z. the ce input enables device for single or ddp . the ce 1 input enables the first ddp device(KFH4G16Q2M) in qdp(kfw8g16q2m) ce2 i chip enable the ce 2 input enables the second ddp device(KFH4G16Q2M) in qdp(kfw8g16q2m) oe i output enable oe -low enables the devices output data buffers during a read cycle. power supply vcc-core / vcc power for onenand core this is the power supply for onenand core. vcc-io / vccq power for onenand i/o this is the power supply for onenand i/o vcc-io / vccq is internally separated from vcc-core / vcc. vss ground for onenand etc. dnu do not use leave it disconnected. these pins are used for testing. nc no connection lead is not internally connected. 2.4 pin description
onenand2g(kfg2g16q2m-debx) flash memory 13 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) bootram statemachine bootloader internal registers (address/command/configuration /status registers) error correction logic dataram0 bufferram nand flash array otp (one block) 2.6 memory array organization the onenand architecture integrates several memory areas on a single chip. 2.6.1 internal (nand ar ray) memory organization the on-chip internal memory is a single-level-cell (slc) nand array used for data storage and code. the internal memory is divi ded into a main area and a spare area. main area the main area is the primary memory array. this main area is divided into blocks of 64 pages. within a block, each page is 2k b and is comprised of 4 sectors. within a page, each sector is 512b and is comprised of 256 words. spare area the spare area is used for invalid block information and ecc storage. spare area internal memory is associated with correspondi ng main area memory. within a block, each page has four 16b sectors of spare area. each spare area sector is 8 words. dataram1 2.5 block diagram 1st block otp host interface a15~a0 dq15~dq0 (block 0) clk oe we rp avd int / int1 rdy ce2 * ce / ce1 int2* * note : ce2 and int2 are only available in qdp device
onenand2g(kfg2g16q2m-debx) flash memory 14 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) internal memory array information internal memory array organization area block page sector main 128kb 2kb 512b spare 4kb 64b 16b 2kb page0 512b 16b 64b page0 2kb page63 64b page63 sector main area spare area block page main area spare area 2kb 64b main area spare area 128kb 4kb page 0 page 63 512b sector0 512b sector1 512b sector2 512b sector3 16b sector0 16b sector1 16b sector2 16b sector3
onenand2g(kfg2g16q2m-debx) flash memory 15 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the on-chip external memory is comprised of 3 buffers used for boot code storage and data buffering. the bootram is a 1kb buffer that receives boot code from the internal memory and makes it available to the host at start up. there are two independent 2kb bi-directional data buffers, dataram0 and dataram1. these dual buffers enable the host to execute simultaneous read-while load, and write-while-program operations after boot up. during boot up, the bootram is used by the host to initialize the main memory, and deliver boot code from nand flash core to host. the external memory is divided into a main area and a spare area. each buffer is the equivalent size of a sector. the main area data is 512b. the spare area data is 16b. external memory array information area bootram dataram0 dataram1 total size 1kb+32b 2kb+64b 2kb+64b number of sectors 2 4 4 sector main 512b 512b 512b spare 16b 16b 16b host otp block nand array boot code (1kb) bootram (1kb) dataram0 (2kb) dataram1 (2kb) external (bufferram) memory internal (nand array) memory 2.6.2 external (bufferram) memory organization
onenand2g(kfg2g16q2m-debx) flash memory 16 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) external memory array organization bootram 0 bootram 1 bootram dataram 1_0 dataram 1_1 dataram 1_2 dataram 1_3 dataram1 ^ main area data spare area data dataram 0_0 dataram 0_1 dataram 0_2 dataram 0_3 dataram0 sector: (512 + 16) byte ^ (512b) (16b)
onenand2g(kfg2g16q2m-debx) flash memory 17 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the following tables are the memory maps for the onenand. 2.7.1 internal (nand array) memory organization the following tables show the internal memory address map in word order. block block address page and sector address size block block address page and sector address size block0 0000h 0000h~00ffh 128kb block32 0020h 0000h~00ffh 128kb block1 0001h 0000h~00ffh 128kb block33 0021h 0000h~00ffh 128kb block2 0002h 0000h~00ffh 128kb block34 0022h 0000h~00ffh 128kb block3 0003h 0000h~00ffh 128kb block35 0023h 0000h~00ffh 128kb block4 0004h 0000h~00ffh 128kb block36 0024h 0000h~00ffh 128kb block5 0005h 0000h~00ffh 128kb block37 0025h 0000h~00ffh 128kb block6 0006h 0000h~00ffh 128kb block38 0026h 0000h~00ffh 128kb block7 0007h 0000h~00ffh 128kb block39 0027h 0000h~00ffh 128kb block8 0008h 0000h~00ffh 128kb block40 0028h 0000h~00ffh 128kb block9 0009h 0000h~00ffh 128kb block41 0029h 0000h~00ffh 128kb block10 000ah 0000h~00ffh 128kb block42 002ah 0000h~00ffh 128kb block11 000bh 0000h~00ffh 128kb block43 002bh 0000h~00ffh 128kb block12 000ch 0000h~00ffh 128kb block44 002ch 0000h~00ffh 128kb block13 000dh 0000h~00ffh 128kb block45 002dh 0000h~00ffh 128kb block14 000eh 0000h~00ffh 128kb block46 002eh 0000h~00ffh 128kb block15 000fh 0000h~00ffh 128kb block47 002fh 0000h~00ffh 128kb block16 0010h 0000h~00ffh 128kb block48 0030h 0000h~00ffh 128kb block17 0011h 0000h~00ffh 128kb block49 0031h 0000h~00ffh 128kb block18 0012h 0000h~00ffh 128kb block50 0032h 0000h~00ffh 128kb block19 0013h 0000h~00ffh 128kb block51 0033h 0000h~00ffh 128kb block20 0014h 0000h~00ffh 128kb block52 0034h 0000h~00ffh 128kb block21 0015h 0000h~00ffh 128kb block53 0035h 0000h~00ffh 128kb block22 0016h 0000h~00ffh 128kb block54 0036h 0000h~00ffh 128kb block23 0017h 0000h~00ffh 128kb block55 0037h 0000h~00ffh 128kb block24 0018h 0000h~00ffh 128kb block56 0038h 0000h~00ffh 128kb block25 0019h 0000h~00ffh 128kb block57 0039h 0000h~00ffh 128kb block26 001ah 0000h~00ffh 128kb block58 003ah 0000h~00ffh 128kb block27 001bh 0000h~00ffh 128kb block59 003bh 0000h~00ffh 128kb block28 001ch 0000h~00ffh 128kb block60 003ch 0000h~00ffh 128kb block29 001dh 0000h~00ffh 128kb block61 003dh 0000h~00ffh 128kb block30 001eh 0000h~00ffh 128kb block62 003eh 0000h~00ffh 128kb block31 001fh 0000h~00ffh 128kb block63 003fh 0000h~00ffh 128kb 2.7 memory map
onenand2g(kfg2g16q2m-debx) flash memory 18 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block64 0040h 0000h~00ffh 128kb block96 0060h 0000h~00ffh 128kb block65 0041h 0000h~00ffh 128kb block97 0061h 0000h~00ffh 128kb block66 0042h 0000h~00ffh 128kb block98 0062h 0000h~00ffh 128kb block67 0043h 0000h~00ffh 128kb block99 0063h 0000h~00ffh 128kb block68 0044h 0000h~00ffh 128kb block100 0064h 0000h~00ffh 128kb block69 0045h 0000h~00ffh 128kb block101 0065h 0000h~00ffh 128kb block70 0046h 0000h~00ffh 128kb block102 0066h 0000h~00ffh 128kb block71 0047h 0000h~00ffh 128kb block103 0067h 0000h~00ffh 128kb block72 0048h 0000h~00ffh 128kb block104 0068h 0000h~00ffh 128kb block73 0049h 0000h~00ffh 128kb block105 0069h 0000h~00ffh 128kb block74 004ah 0000h~00ffh 128kb block106 006ah 0000h~00ffh 128kb block75 004bh 0000h~00ffh 128kb block107 006bh 0000h~00ffh 128kb block76 004ch 0000h~00ffh 128kb block108 006ch 0000h~00ffh 128kb block77 004dh 0000h~00ffh 128kb block109 006dh 0000h~00ffh 128kb block78 004eh 0000h~00ffh 128kb block110 006eh 0000h~00ffh 128kb block79 004fh 0000h~00ffh 128kb block111 006fh 0000h~00ffh 128kb block80 0050h 0000h~00ffh 128kb block112 0070h 0000h~00ffh 128kb block81 0051h 0000h~00ffh 128kb block113 0071h 0000h~00ffh 128kb block82 0052h 0000h~00ffh 128kb block114 0072h 0000h~00ffh 128kb block83 0053h 0000h~00ffh 128kb block115 0073h 0000h~00ffh 128kb block84 0054h 0000h~00ffh 128kb block116 0074h 0000h~00ffh 128kb block85 0055h 0000h~00ffh 128kb block117 0075h 0000h~00ffh 128kb block86 0056h 0000h~00ffh 128kb block118 0076h 0000h~00ffh 128kb block87 0057h 0000h~00ffh 128kb block119 0077h 0000h~00ffh 128kb block88 0058h 0000h~00ffh 128kb block120 0078h 0000h~00ffh 128kb block89 0059h 0000h~00ffh 128kb block121 0079h 0000h~00ffh 128kb block90 005ah 0000h~00ffh 128kb block122 007ah 0000h~00ffh 128kb block91 005bh 0000h~00ffh 128kb block123 007bh 0000h~00ffh 128kb block92 005ch 0000h~00ffh 128kb block124 007ch 0000h~00ffh 128kb block93 005dh 0000h~00ffh 128kb block125 007dh 0000h~00ffh 128kb block94 005eh 0000h~00ffh 128kb block126 007eh 0000h~00ffh 128kb block95 005fh 0000h~00ffh 128kb block127 007fh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 19 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block128 0080h 0000h~00ffh 128kb block160 00a0h 0000h~00ffh 128kb block129 0081h 0000h~00ffh 128kb block161 00a1h 0000h~00ffh 128kb block130 0082h 0000h~00ffh 128kb block162 00a2h 0000h~00ffh 128kb block131 0083h 0000h~00ffh 128kb block163 00a3h 0000h~00ffh 128kb block132 0084h 0000h~00ffh 128kb block164 00a4h 0000h~00ffh 128kb block133 0085h 0000h~00ffh 128kb block165 00a5h 0000h~00ffh 128kb block134 0086h 0000h~00ffh 128kb block166 00a6h 0000h~00ffh 128kb block135 0087h 0000h~00ffh 128kb block167 00a7h 0000h~00ffh 128kb block136 0088h 0000h~00ffh 128kb block168 00a8h 0000h~00ffh 128kb block137 0089h 0000h~00ffh 128kb block169 00a9h 0000h~00ffh 128kb block138 008ah 0000h~00ffh 128kb block170 00aah 0000h~00ffh 128kb block139 008bh 0000h~00ffh 128kb block171 00abh 0000h~00ffh 128kb block140 008ch 0000h~00ffh 128kb block172 00ach 0000h~00ffh 128kb block141 008dh 0000h~00ffh 128kb block173 00adh 0000h~00ffh 128kb block142 008eh 0000h~00ffh 128kb block174 00aeh 0000h~00ffh 128kb block143 008fh 0000h~00ffh 128kb block175 00afh 0000h~00ffh 128kb block144 0090h 0000h~00ffh 128kb block176 00b0h 0000h~00ffh 128kb block145 0091h 0000h~00ffh 128kb block177 00b1h 0000h~00ffh 128kb block146 0092h 0000h~00ffh 128kb block178 00b2h 0000h~00ffh 128kb block147 0093h 0000h~00ffh 128kb block179 00b3h 0000h~00ffh 128kb block148 0094h 0000h~00ffh 128kb block180 00b4h 0000h~00ffh 128kb block149 0095h 0000h~00ffh 128kb block181 00b5h 0000h~00ffh 128kb block150 0096h 0000h~00ffh 128kb block182 00b6h 0000h~00ffh 128kb block151 0097h 0000h~00ffh 128kb block183 00b7h 0000h~00ffh 128kb block152 0098h 0000h~00ffh 128kb block184 00b8h 0000h~00ffh 128kb block153 0099h 0000h~00ffh 128kb block185 00b9h 0000h~00ffh 128kb block154 009ah 0000h~00ffh 128kb block186 00bah 0000h~00ffh 128kb block155 009bh 0000h~00ffh 128kb block187 00bbh 0000h~00ffh 128kb block156 009ch 0000h~00ffh 128kb block188 00bch 0000h~00ffh 128kb block157 009dh 0000h~00ffh 128kb block189 00bdh 0000h~00ffh 128kb block158 009eh 0000h~00ffh 128kb block190 00beh 0000h~00ffh 128kb block159 009fh 0000h~00ffh 128kb block191 00bfh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 20 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block192 00c0h 0000h~00ffh 128kb block224 00e0h 0000h~00ffh 128kb block193 00c1h 0000h~00ffh 128kb block225 00e1h 0000h~00ffh 128kb block194 00c2h 0000h~00ffh 128kb block226 00e2h 0000h~00ffh 128kb block195 00c3h 0000h~00ffh 128kb block227 00e3h 0000h~00ffh 128kb block196 00c4h 0000h~00ffh 128kb block228 00e4h 0000h~00ffh 128kb block197 00c5h 0000h~00ffh 128kb block229 00e5h 0000h~00ffh 128kb block198 00c6h 0000h~00ffh 128kb block230 00e6h 0000h~00ffh 128kb block199 00c7h 0000h~00ffh 128kb block231 00e7h 0000h~00ffh 128kb block200 00c8h 0000h~00ffh 128kb block232 00e8h 0000h~00ffh 128kb block201 00c9h 0000h~00ffh 128kb block233 00e9h 0000h~00ffh 128kb block202 00cah 0000h~00ffh 128kb block234 00eah 0000h~00ffh 128kb block203 00cbh 0000h~00ffh 128kb block235 00ebh 0000h~00ffh 128kb block204 00cch 0000h~00ffh 128kb block236 00ech 0000h~00ffh 128kb block205 00cdh 0000h~00ffh 128kb block237 00edh 0000h~00ffh 128kb block206 00ceh 0000h~00ffh 128kb block238 00eeh 0000h~00ffh 128kb block207 00cfh 0000h~00ffh 128kb block239 00efh 0000h~00ffh 128kb block208 00d0h 0000h~00ffh 128kb block240 00f0h 0000h~00ffh 128kb block209 00d1h 0000h~00ffh 128kb block241 00f1h 0000h~00ffh 128kb block210 00d2h 0000h~00ffh 128kb block242 00f2h 0000h~00ffh 128kb block211 00d3h 0000h~00ffh 128kb block243 00f3h 0000h~00ffh 128kb block212 00d4h 0000h~00ffh 128kb block244 00f4h 0000h~00ffh 128kb block213 00d5h 0000h~00ffh 128kb block245 00f5h 0000h~00ffh 128kb block214 00d6h 0000h~00ffh 128kb block246 00f6h 0000h~00ffh 128kb block215 00d7h 0000h~00ffh 128kb block247 00f7h 0000h~00ffh 128kb block216 00d8h 0000h~00ffh 128kb block248 00f8h 0000h~00ffh 128kb block217 00d9h 0000h~00ffh 128kb block249 00f9h 0000h~00ffh 128kb block218 00dah 0000h~00ffh 128kb block250 00fah 0000h~00ffh 128kb block219 00dbh 0000h~00ffh 128kb block251 00fbh 0000h~00ffh 128kb block220 00dch 0000h~00ffh 128kb block252 00fch 0000h~00ffh 128kb block221 00ddh 0000h~00ffh 128kb block253 00fdh 0000h~00ffh 128kb block222 00deh 0000h~00ffh 128kb block254 00feh 0000h~00ffh 128kb block223 00dfh 0000h~00ffh 128kb block255 00ffh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 21 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block256 0100h 0000h~00ffh 128kb block288 0120h 0000h~00ffh 128kb block257 0101h 0000h~00ffh 128kb block289 0121h 0000h~00ffh 128kb block258 0102h 0000h~00ffh 128kb block290 0122h 0000h~00ffh 128kb block259 0103h 0000h~00ffh 128kb block291 0123h 0000h~00ffh 128kb block260 0104h 0000h~00ffh 128kb block292 0124h 0000h~00ffh 128kb block261 0105h 0000h~00ffh 128kb block293 0125h 0000h~00ffh 128kb block262 0106h 0000h~00ffh 128kb block294 0126h 0000h~00ffh 128kb block263 0107h 0000h~00ffh 128kb block295 0127h 0000h~00ffh 128kb block264 0108h 0000h~00ffh 128kb block296 0128h 0000h~00ffh 128kb block265 0109h 0000h~00ffh 128kb block297 0129h 0000h~00ffh 128kb block266 010ah 0000h~00ffh 128kb block298 012ah 0000h~00ffh 128kb block267 010bh 0000h~00ffh 128kb block299 012bh 0000h~00ffh 128kb block268 010ch 0000h~00ffh 128kb block300 012ch 0000h~00ffh 128kb block269 010dh 0000h~00ffh 128kb block301 012dh 0000h~00ffh 128kb block270 010eh 0000h~00ffh 128kb block302 012eh 0000h~00ffh 128kb block271 010fh 0000h~00ffh 128kb block303 012fh 0000h~00ffh 128kb block272 0110h 0000h~00ffh 128kb block304 0130h 0000h~00ffh 128kb block273 0111h 0000h~00ffh 128kb block305 0131h 0000h~00ffh 128kb block274 0112h 0000h~00ffh 128kb block306 0132h 0000h~00ffh 128kb block275 0113h 0000h~00ffh 128kb block307 0133h 0000h~00ffh 128kb block276 0114h 0000h~00ffh 128kb block308 0134h 0000h~00ffh 128kb block277 0115h 0000h~00ffh 128kb block309 0135h 0000h~00ffh 128kb block278 0116h 0000h~00ffh 128kb block310 0136h 0000h~00ffh 128kb block279 0117h 0000h~00ffh 128kb block311 0137h 0000h~00ffh 128kb block280 0118h 0000h~00ffh 128kb block312 0138h 0000h~00ffh 128kb block281 0119h 0000h~00ffh 128kb block313 0139h 0000h~00ffh 128kb block282 011ah 0000h~00ffh 128kb block314 013ah 0000h~00ffh 128kb block283 011bh 0000h~00ffh 128kb block315 013bh 0000h~00ffh 128kb block284 011ch 0000h~00ffh 128kb block316 013ch 0000h~00ffh 128kb block285 011dh 0000h~00ffh 128kb block317 013dh 0000h~00ffh 128kb block286 011eh 0000h~00ffh 128kb block318 013eh 0000h~00ffh 128kb block287 011fh 0000h~00ffh 128kb block319 013fh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 22 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block320 0140h 0000h~00ffh 128kb block352 0160h 0000h~00ffh 128kb block321 0141h 0000h~00ffh 128kb block353 0161h 0000h~00ffh 128kb block322 0142h 0000h~00ffh 128kb block354 0162h 0000h~00ffh 128kb block323 0143h 0000h~00ffh 128kb block355 0163h 0000h~00ffh 128kb block324 0144h 0000h~00ffh 128kb block356 0164h 0000h~00ffh 128kb block325 0145h 0000h~00ffh 128kb block357 0165h 0000h~00ffh 128kb block326 0146h 0000h~00ffh 128kb block358 0166h 0000h~00ffh 128kb block327 0147h 0000h~00ffh 128kb block359 0167h 0000h~00ffh 128kb block328 0148h 0000h~00ffh 128kb block360 0168h 0000h~00ffh 128kb block329 0149h 0000h~00ffh 128kb block361 0169h 0000h~00ffh 128kb block330 014ah 0000h~00ffh 128kb block362 016ah 0000h~00ffh 128kb block331 014bh 0000h~00ffh 128kb block363 016bh 0000h~00ffh 128kb block332 014ch 0000h~00ffh 128kb block364 016ch 0000h~00ffh 128kb block333 014dh 0000h~00ffh 128kb block365 016dh 0000h~00ffh 128kb block334 014eh 0000h~00ffh 128kb block366 016eh 0000h~00ffh 128kb block335 014fh 0000h~00ffh 128kb block367 016fh 0000h~00ffh 128kb block336 0150h 0000h~00ffh 128kb block368 0170h 0000h~00ffh 128kb block337 0151h 0000h~00ffh 128kb block369 0171h 0000h~00ffh 128kb block338 0152h 0000h~00ffh 128kb block370 0172h 0000h~00ffh 128kb block339 0153h 0000h~00ffh 128kb block371 0173h 0000h~00ffh 128kb block340 0154h 0000h~00ffh 128kb block372 0174h 0000h~00ffh 128kb block341 0155h 0000h~00ffh 128kb block373 0175h 0000h~00ffh 128kb block342 0156h 0000h~00ffh 128kb block374 0176h 0000h~00ffh 128kb block343 0157h 0000h~00ffh 128kb block375 0177h 0000h~00ffh 128kb block344 0158h 0000h~00ffh 128kb block376 0178h 0000h~00ffh 128kb block345 0159h 0000h~00ffh 128kb block377 0179h 0000h~00ffh 128kb block346 015ah 0000h~00ffh 128kb block378 017ah 0000h~00ffh 128kb block347 015bh 0000h~00ffh 128kb block379 017bh 0000h~00ffh 128kb block348 015ch 0000h~00ffh 128kb block380 017ch 0000h~00ffh 128kb block349 015dh 0000h~00ffh 128kb block381 017dh 0000h~00ffh 128kb block350 015eh 0000h~00ffh 128kb block382 017eh 0000h~00ffh 128kb block351 015fh 0000h~00ffh 128kb block383 017fh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 23 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block384 0180h 0000h~00ffh 128kb block416 01a0h 0000h~00ffh 128kb block385 0181h 0000h~00ffh 128kb block417 01a1h 0000h~00ffh 128kb block386 0182h 0000h~00ffh 128kb block418 01a2h 0000h~00ffh 128kb block387 0183h 0000h~00ffh 128kb block419 01a3h 0000h~00ffh 128kb block388 0184h 0000h~00ffh 128kb block420 01a4h 0000h~00ffh 128kb block389 0185h 0000h~00ffh 128kb block421 01a5h 0000h~00ffh 128kb block390 0186h 0000h~00ffh 128kb block422 01a6h 0000h~00ffh 128kb block391 0187h 0000h~00ffh 128kb block423 01a7h 0000h~00ffh 128kb block392 0188h 0000h~00ffh 128kb block424 01a8h 0000h~00ffh 128kb block393 0189h 0000h~00ffh 128kb block425 01a9h 0000h~00ffh 128kb block394 018ah 0000h~00ffh 128kb block426 01aah 0000h~00ffh 128kb block395 018bh 0000h~00ffh 128kb block427 01abh 0000h~00ffh 128kb block396 018ch 0000h~00ffh 128kb block428 01ach 0000h~00ffh 128kb block397 018dh 0000h~00ffh 128kb block429 01adh 0000h~00ffh 128kb block398 018eh 0000h~00ffh 128kb block430 01aeh 0000h~00ffh 128kb block399 018fh 0000h~00ffh 128kb block431 01afh 0000h~00ffh 128kb block400 0190h 0000h~00ffh 128kb block432 01b0h 0000h~00ffh 128kb block401 0191h 0000h~00ffh 128kb block433 01b1h 0000h~00ffh 128kb block402 0192h 0000h~00ffh 128kb block434 01b2h 0000h~00ffh 128kb block403 0193h 0000h~00ffh 128kb block435 01b3h 0000h~00ffh 128kb block404 0194h 0000h~00ffh 128kb block436 01b4h 0000h~00ffh 128kb block405 0195h 0000h~00ffh 128kb block437 01b5h 0000h~00ffh 128kb block406 0196h 0000h~00ffh 128kb block438 01b6h 0000h~00ffh 128kb block407 0197h 0000h~00ffh 128kb block439 01b7h 0000h~00ffh 128kb block408 0198h 0000h~00ffh 128kb block440 01b8h 0000h~00ffh 128kb block409 0199h 0000h~00ffh 128kb block441 01b9h 0000h~00ffh 128kb block410 019ah 0000h~00ffh 128kb block442 01bah 0000h~00ffh 128kb block411 019bh 0000h~00ffh 128kb block443 01bbh 0000h~00ffh 128kb block412 019ch 0000h~00ffh 128kb block444 01bch 0000h~00ffh 128kb block413 019dh 0000h~00ffh 128kb block445 01bdh 0000h~00ffh 128kb block414 019eh 0000h~00ffh 128kb block446 01beh 0000h~00ffh 128kb block415 019fh 0000h~00ffh 128kb block447 01bfh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 24 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block448 01c0h 0000h~00ffh 128kb block480 01e0h 0000h~00ffh 128kb block449 01c1h 0000h~00ffh 128kb block481 01e1h 0000h~00ffh 128kb block450 01c2h 0000h~00ffh 128kb block482 01e2h 0000h~00ffh 128kb block451 01c3h 0000h~00ffh 128kb block483 01e3h 0000h~00ffh 128kb block452 01c4h 0000h~00ffh 128kb block484 01e4h 0000h~00ffh 128kb block453 01c5h 0000h~00ffh 128kb block485 01e5h 0000h~00ffh 128kb block454 01c6h 0000h~00ffh 128kb block486 01e6h 0000h~00ffh 128kb block455 01c7h 0000h~00ffh 128kb block487 01e7h 0000h~00ffh 128kb block456 01c8h 0000h~00ffh 128kb block488 01e8h 0000h~00ffh 128kb block457 01c9h 0000h~00ffh 128kb block489 01e9h 0000h~00ffh 128kb block458 01cah 0000h~00ffh 128kb block490 01eah 0000h~00ffh 128kb block459 01cbh 0000h~00ffh 128kb block491 01ebh 0000h~00ffh 128kb block460 01cch 0000h~00ffh 128kb block492 01ech 0000h~00ffh 128kb block461 01cdh 0000h~00ffh 128kb block493 01edh 0000h~00ffh 128kb block462 01ceh 0000h~00ffh 128kb block494 01eeh 0000h~00ffh 128kb block463 01cfh 0000h~00ffh 128kb block495 01efh 0000h~00ffh 128kb block464 01d0h 0000h~00ffh 128kb block496 01f0h 0000h~00ffh 128kb block465 01d1h 0000h~00ffh 128kb block497 01f1h 0000h~00ffh 128kb block466 01d2h 0000h~00ffh 128kb block498 01f2h 0000h~00ffh 128kb block467 01d3h 0000h~00ffh 128kb block499 01f3h 0000h~00ffh 128kb block468 01d4h 0000h~00ffh 128kb block500 01f4h 0000h~00ffh 128kb block469 01d5h 0000h~00ffh 128kb block501 01f5h 0000h~00ffh 128kb block470 01d6h 0000h~00ffh 128kb block502 01f6h 0000h~00ffh 128kb block471 01d7h 0000h~00ffh 128kb block503 01f7h 0000h~00ffh 128kb block472 01d8h 0000h~00ffh 128kb block504 01f8h 0000h~00ffh 128kb block473 01d9h 0000h~00ffh 128kb block505 01f9h 0000h~00ffh 128kb block474 01dah 0000h~00ffh 128kb block506 01fah 0000h~00ffh 128kb block475 01dbh 0000h~00ffh 128kb block507 01fbh 0000h~00ffh 128kb block476 01dch 0000h~00ffh 128kb block508 01fch 0000h~00ffh 128kb block477 01ddh 0000h~00ffh 128kb block509 01fdh 0000h~00ffh 128kb block478 01deh 0000h~00ffh 128kb block510 01feh 0000h~00ffh 128kb block479 01dfh 0000h~00ffh 128kb block511 01ffh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 25 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block512 0200h 0000h~00ffh 128kb block544 0220h 0000h~00ffh 128kb block513 0201h 0000h~00ffh 128kb block545 0221h 0000h~00ffh 128kb block514 0202h 0000h~00ffh 128kb block546 0222h 0000h~00ffh 128kb block515 0203h 0000h~00ffh 128kb block547 0223h 0000h~00ffh 128kb block516 0204h 0000h~00ffh 128kb block548 0224h 0000h~00ffh 128kb block517 0205h 0000h~00ffh 128kb block549 0225h 0000h~00ffh 128kb block518 0206h 0000h~00ffh 128kb block550 0226h 0000h~00ffh 128kb block519 0207h 0000h~00ffh 128kb block551 0227h 0000h~00ffh 128kb block520 0208h 0000h~00ffh 128kb block552 0228h 0000h~00ffh 128kb block521 0209h 0000h~00ffh 128kb block553 0229h 0000h~00ffh 128kb block522 020ah 0000h~00ffh 128kb block554 022ah 0000h~00ffh 128kb block523 020bh 0000h~00ffh 128kb block555 022bh 0000h~00ffh 128kb block524 020ch 0000h~00ffh 128kb block556 022ch 0000h~00ffh 128kb block525 020dh 0000h~00ffh 128kb block557 022dh 0000h~00ffh 128kb block526 020eh 0000h~00ffh 128kb block558 022eh 0000h~00ffh 128kb block527 020fh 0000h~00ffh 128kb block559 022fh 0000h~00ffh 128kb block528 0210h 0000h~00ffh 128kb block560 0230h 0000h~00ffh 128kb block529 0211h 0000h~00ffh 128kb block561 0231h 0000h~00ffh 128kb block530 0212h 0000h~00ffh 128kb block562 0232h 0000h~00ffh 128kb block531 0213h 0000h~00ffh 128kb block563 0233h 0000h~00ffh 128kb block532 0214h 0000h~00ffh 128kb block564 0234h 0000h~00ffh 128kb block533 0215h 0000h~00ffh 128kb block565 0235h 0000h~00ffh 128kb block534 0216h 0000h~00ffh 128kb block566 0236h 0000h~00ffh 128kb block535 0217h 0000h~00ffh 128kb block567 0237h 0000h~00ffh 128kb block536 0218h 0000h~00ffh 128kb block568 0238h 0000h~00ffh 128kb block537 0219h 0000h~00ffh 128kb block569 0239h 0000h~00ffh 128kb block538 021ah 0000h~00ffh 128kb block570 023ah 0000h~00ffh 128kb block539 021bh 0000h~00ffh 128kb block571 023bh 0000h~00ffh 128kb block540 021ch 0000h~00ffh 128kb block572 023ch 0000h~00ffh 128kb block541 021dh 0000h~00ffh 128kb block573 023dh 0000h~00ffh 128kb block542 021eh 0000h~00ffh 128kb block574 023eh 0000h~00ffh 128kb block543 021fh 0000h~00ffh 128kb block575 023fh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 26 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block576 0240h 0000h~00ffh 128kb block608 0260h 0000h~00ffh 128kb block577 0241h 0000h~00ffh 128kb block609 0261h 0000h~00ffh 128kb block578 0242h 0000h~00ffh 128kb block610 0262h 0000h~00ffh 128kb block579 0243h 0000h~00ffh 128kb block611 0263h 0000h~00ffh 128kb block580 0244h 0000h~00ffh 128kb block612 0264h 0000h~00ffh 128kb block581 0245h 0000h~00ffh 128kb block613 0265h 0000h~00ffh 128kb block582 0246h 0000h~00ffh 128kb block614 0266h 0000h~00ffh 128kb block583 0247h 0000h~00ffh 128kb block615 0267h 0000h~00ffh 128kb block584 0248h 0000h~00ffh 128kb block616 0268h 0000h~00ffh 128kb block585 0249h 0000h~00ffh 128kb block617 0269h 0000h~00ffh 128kb block586 024ah 0000h~00ffh 128kb block618 026ah 0000h~00ffh 128kb block587 024bh 0000h~00ffh 128kb block619 026bh 0000h~00ffh 128kb block588 024ch 0000h~00ffh 128kb block620 026ch 0000h~00ffh 128kb block589 024dh 0000h~00ffh 128kb block621 026dh 0000h~00ffh 128kb block590 024eh 0000h~00ffh 128kb block622 026eh 0000h~00ffh 128kb block591 024fh 0000h~00ffh 128kb block623 026fh 0000h~00ffh 128kb block592 0250h 0000h~00ffh 128kb block624 0270h 0000h~00ffh 128kb block593 0251h 0000h~00ffh 128kb block625 0271h 0000h~00ffh 128kb block594 0252h 0000h~00ffh 128kb block626 0272h 0000h~00ffh 128kb block595 0253h 0000h~00ffh 128kb block627 0273h 0000h~00ffh 128kb block596 0254h 0000h~00ffh 128kb block628 0274h 0000h~00ffh 128kb block597 0255h 0000h~00ffh 128kb block629 0275h 0000h~00ffh 128kb block598 0256h 0000h~00ffh 128kb block630 0276h 0000h~00ffh 128kb block599 0257h 0000h~00ffh 128kb block631 0277h 0000h~00ffh 128kb block600 0258h 0000h~00ffh 128kb block632 0278h 0000h~00ffh 128kb block601 0259h 0000h~00ffh 128kb block633 0279h 0000h~00ffh 128kb block602 025ah 0000h~00ffh 128kb block634 027ah 0000h~00ffh 128kb block603 025bh 0000h~00ffh 128kb block635 027bh 0000h~00ffh 128kb block604 025ch 0000h~00ffh 128kb block636 027ch 0000h~00ffh 128kb block605 025dh 0000h~00ffh 128kb block637 027dh 0000h~00ffh 128kb block606 025eh 0000h~00ffh 128kb block638 027eh 0000h~00ffh 128kb block607 025fh 0000h~00ffh 128kb block639 027fh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 27 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block640 0280h 0000h~00ffh 128kb block672 02a0h 0000h~00ffh 128kb block641 0281h 0000h~00ffh 128kb block673 02a1h 0000h~00ffh 128kb block642 0282h 0000h~00ffh 128kb block674 02a2h 0000h~00ffh 128kb block643 0283h 0000h~00ffh 128kb block675 02a3h 0000h~00ffh 128kb block644 0284h 0000h~00ffh 128kb block676 02a4h 0000h~00ffh 128kb block645 0285h 0000h~00ffh 128kb block677 02a5h 0000h~00ffh 128kb block646 0286h 0000h~00ffh 128kb block678 02a6h 0000h~00ffh 128kb block647 0287h 0000h~00ffh 128kb block679 02a7h 0000h~00ffh 128kb block648 0288h 0000h~00ffh 128kb block680 02a8h 0000h~00ffh 128kb block649 0289h 0000h~00ffh 128kb block681 02a9h 0000h~00ffh 128kb block650 028ah 0000h~00ffh 128kb block682 02aah 0000h~00ffh 128kb block651 028bh 0000h~00ffh 128kb block683 02abh 0000h~00ffh 128kb block652 028ch 0000h~00ffh 128kb block684 02ach 0000h~00ffh 128kb block653 028dh 0000h~00ffh 128kb block685 02adh 0000h~00ffh 128kb block654 028eh 0000h~00ffh 128kb block686 02aeh 0000h~00ffh 128kb block655 028fh 0000h~00ffh 128kb block687 02afh 0000h~00ffh 128kb block656 0290h 0000h~00ffh 128kb block688 02b0h 0000h~00ffh 128kb block657 0291h 0000h~00ffh 128kb block689 02b1h 0000h~00ffh 128kb block658 0292h 0000h~00ffh 128kb block690 02b2h 0000h~00ffh 128kb block659 0293h 0000h~00ffh 128kb block691 02b3h 0000h~00ffh 128kb block660 0294h 0000h~00ffh 128kb block692 02b4h 0000h~00ffh 128kb block661 0295h 0000h~00ffh 128kb block693 02b5h 0000h~00ffh 128kb block662 0296h 0000h~00ffh 128kb block694 02b6h 0000h~00ffh 128kb block663 0297h 0000h~00ffh 128kb block695 02b7h 0000h~00ffh 128kb block664 0298h 0000h~00ffh 128kb block696 02b8h 0000h~00ffh 128kb block665 0299h 0000h~00ffh 128kb block697 02b9h 0000h~00ffh 128kb block666 029ah 0000h~00ffh 128kb block698 02bah 0000h~00ffh 128kb block667 029bh 0000h~00ffh 128kb block699 02bbh 0000h~00ffh 128kb block668 029ch 0000h~00ffh 128kb block700 02bch 0000h~00ffh 128kb block669 029dh 0000h~00ffh 128kb block701 02bdh 0000h~00ffh 128kb block670 029eh 0000h~00ffh 128kb block702 02beh 0000h~00ffh 128kb block671 029fh 0000h~00ffh 128kb block703 02bfh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 28 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block704 02c0h 0000h~00ffh 128kb block736 02e0h 0000h~00ffh 128kb block705 02c1h 0000h~00ffh 128kb block737 02e1h 0000h~00ffh 128kb block706 02c2h 0000h~00ffh 128kb block738 02e2h 0000h~00ffh 128kb block707 02c3h 0000h~00ffh 128kb block739 02e3h 0000h~00ffh 128kb block708 02c4h 0000h~00ffh 128kb block740 02e4h 0000h~00ffh 128kb block709 02c5h 0000h~00ffh 128kb block741 02e5h 0000h~00ffh 128kb block710 02c6h 0000h~00ffh 128kb block742 02e6h 0000h~00ffh 128kb block711 02c7h 0000h~00ffh 128kb block743 02e7h 0000h~00ffh 128kb block712 02c8h 0000h~00ffh 128kb block744 02e8h 0000h~00ffh 128kb block713 02c9h 0000h~00ffh 128kb block745 02e9h 0000h~00ffh 128kb block714 02cah 0000h~00ffh 128kb block746 02eah 0000h~00ffh 128kb block715 02cbh 0000h~00ffh 128kb block747 02ebh 0000h~00ffh 128kb block716 02cch 0000h~00ffh 128kb block748 02ech 0000h~00ffh 128kb block717 02cdh 0000h~00ffh 128kb block749 02edh 0000h~00ffh 128kb block718 02ceh 0000h~00ffh 128kb block750 02eeh 0000h~00ffh 128kb block719 02cfh 0000h~00ffh 128kb block751 02efh 0000h~00ffh 128kb block720 02d0h 0000h~00ffh 128kb block752 02f0h 0000h~00ffh 128kb block721 02d1h 0000h~00ffh 128kb block753 02f1h 0000h~00ffh 128kb block722 02d2h 0000h~00ffh 128kb block754 02f2h 0000h~00ffh 128kb block723 02d3h 0000h~00ffh 128kb block755 02f3h 0000h~00ffh 128kb block724 02d4h 0000h~00ffh 128kb block756 02f4h 0000h~00ffh 128kb block725 02d5h 0000h~00ffh 128kb block757 02f5h 0000h~00ffh 128kb block726 02d6h 0000h~00ffh 128kb block758 02f6h 0000h~00ffh 128kb block727 02d7h 0000h~00ffh 128kb block759 02f7h 0000h~00ffh 128kb block728 02d8h 0000h~00ffh 128kb block760 02f8h 0000h~00ffh 128kb block729 02d9h 0000h~00ffh 128kb block761 02f9h 0000h~00ffh 128kb block730 02dah 0000h~00ffh 128kb block762 02fah 0000h~00ffh 128kb block731 02dbh 0000h~00ffh 128kb block763 02fbh 0000h~00ffh 128kb block732 02dch 0000h~00ffh 128kb block764 02fch 0000h~00ffh 128kb block733 02ddh 0000h~00ffh 128kb block765 02fdh 0000h~00ffh 128kb block734 02deh 0000h~00ffh 128kb block766 02feh 0000h~00ffh 128kb block735 02dfh 0000h~00ffh 128kb block767 02ffh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 29 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block768 0300h 0000h~00ffh 128kb block800 0320h 0000h~00ffh 128kb block769 0301h 0000h~00ffh 128kb block801 0321h 0000h~00ffh 128kb block770 0302h 0000h~00ffh 128kb block802 0322h 0000h~00ffh 128kb block771 0303h 0000h~00ffh 128kb block803 0323h 0000h~00ffh 128kb block772 0304h 0000h~00ffh 128kb block804 0324h 0000h~00ffh 128kb block773 0305h 0000h~00ffh 128kb block805 0325h 0000h~00ffh 128kb block774 0306h 0000h~00ffh 128kb block806 0326h 0000h~00ffh 128kb block775 0307h 0000h~00ffh 128kb block807 0327h 0000h~00ffh 128kb block776 0308h 0000h~00ffh 128kb block808 0328h 0000h~00ffh 128kb block777 0309h 0000h~00ffh 128kb block809 0329h 0000h~00ffh 128kb block778 030ah 0000h~00ffh 128kb block810 032ah 0000h~00ffh 128kb block779 030bh 0000h~00ffh 128kb block811 032bh 0000h~00ffh 128kb block780 030ch 0000h~00ffh 128kb block812 032ch 0000h~00ffh 128kb block781 030dh 0000h~00ffh 128kb block813 032dh 0000h~00ffh 128kb block782 030eh 0000h~00ffh 128kb block814 032eh 0000h~00ffh 128kb block783 030fh 0000h~00ffh 128kb block815 032fh 0000h~00ffh 128kb block784 0310h 0000h~00ffh 128kb block816 0330h 0000h~00ffh 128kb block785 0311h 0000h~00ffh 128kb block817 0331h 0000h~00ffh 128kb block786 0312h 0000h~00ffh 128kb block818 0332h 0000h~00ffh 128kb block787 0313h 0000h~00ffh 128kb block819 0333h 0000h~00ffh 128kb block788 0314h 0000h~00ffh 128kb block820 0334h 0000h~00ffh 128kb block789 0315h 0000h~00ffh 128kb block821 0335h 0000h~00ffh 128kb block790 0316h 0000h~00ffh 128kb block822 0336h 0000h~00ffh 128kb block791 0317h 0000h~00ffh 128kb block823 0337h 0000h~00ffh 128kb block792 0318h 0000h~00ffh 128kb block824 0338h 0000h~00ffh 128kb block793 0319h 0000h~00ffh 128kb block825 0339h 0000h~00ffh 128kb block794 031ah 0000h~00ffh 128kb block826 033ah 0000h~00ffh 128kb block795 031bh 0000h~00ffh 128kb block827 033bh 0000h~00ffh 128kb block796 031ch 0000h~00ffh 128kb block828 033ch 0000h~00ffh 128kb block797 031dh 0000h~00ffh 128kb block829 033dh 0000h~00ffh 128kb block798 031eh 0000h~00ffh 128kb block830 033eh 0000h~00ffh 128kb block799 031fh 0000h~00ffh 128kb block831 033fh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 30 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block832 0340h 0000h~00ffh 128kb block864 0360h 0000h~00ffh 128kb block833 0341h 0000h~00ffh 128kb block865 0361h 0000h~00ffh 128kb block834 0342h 0000h~00ffh 128kb block866 0362h 0000h~00ffh 128kb block835 0343h 0000h~00ffh 128kb block867 0363h 0000h~00ffh 128kb block836 0344h 0000h~00ffh 128kb block868 0364h 0000h~00ffh 128kb block837 0345h 0000h~00ffh 128kb block869 0365h 0000h~00ffh 128kb block838 0346h 0000h~00ffh 128kb block870 0366h 0000h~00ffh 128kb block839 0347h 0000h~00ffh 128kb block871 0367h 0000h~00ffh 128kb block840 0348h 0000h~00ffh 128kb block872 0368h 0000h~00ffh 128kb block841 0349h 0000h~00ffh 128kb block873 0369h 0000h~00ffh 128kb block842 034ah 0000h~00ffh 128kb block874 036ah 0000h~00ffh 128kb block843 034bh 0000h~00ffh 128kb block875 036bh 0000h~00ffh 128kb block844 034ch 0000h~00ffh 128kb block876 036ch 0000h~00ffh 128kb block845 034dh 0000h~00ffh 128kb block877 036dh 0000h~00ffh 128kb block846 034eh 0000h~00ffh 128kb block878 036eh 0000h~00ffh 128kb block847 034fh 0000h~00ffh 128kb block879 036fh 0000h~00ffh 128kb block848 0350h 0000h~00ffh 128kb block880 0370h 0000h~00ffh 128kb block849 0351h 0000h~00ffh 128kb block881 0371h 0000h~00ffh 128kb block850 0352h 0000h~00ffh 128kb block882 0372h 0000h~00ffh 128kb block851 0353h 0000h~00ffh 128kb block883 0373h 0000h~00ffh 128kb block852 0354h 0000h~00ffh 128kb block884 0374h 0000h~00ffh 128kb block853 0355h 0000h~00ffh 128kb block885 0375h 0000h~00ffh 128kb block854 0356h 0000h~00ffh 128kb block886 0376h 0000h~00ffh 128kb block855 0357h 0000h~00ffh 128kb block887 0377h 0000h~00ffh 128kb block856 0358h 0000h~00ffh 128kb block888 0378h 0000h~00ffh 128kb block857 0359h 0000h~00ffh 128kb block889 0379h 0000h~00ffh 128kb block858 035ah 0000h~00ffh 128kb block890 037ah 0000h~00ffh 128kb block859 035bh 0000h~00ffh 128kb block891 037bh 0000h~00ffh 128kb block860 035ch 0000h~00ffh 128kb block892 037ch 0000h~00ffh 128kb block861 035dh 0000h~00ffh 128kb block893 037dh 0000h~00ffh 128kb block862 035eh 0000h~00ffh 128kb block894 037eh 0000h~00ffh 128kb block863 035fh 0000h~00ffh 128kb block895 037fh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 31 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block896 0380h 0000h~00ffh 128kb block928 03a0h 0000h~00ffh 128kb block897 0381h 0000h~00ffh 128kb block929 03a1h 0000h~00ffh 128kb block898 0382h 0000h~00ffh 128kb block930 03a2h 0000h~00ffh 128kb block899 0383h 0000h~00ffh 128kb block931 03a3h 0000h~00ffh 128kb block900 0384h 0000h~00ffh 128kb block932 03a4h 0000h~00ffh 128kb block901 0385h 0000h~00ffh 128kb block933 03a5h 0000h~00ffh 128kb block902 0386h 0000h~00ffh 128kb block934 03a6h 0000h~00ffh 128kb block903 0387h 0000h~00ffh 128kb block935 03a7h 0000h~00ffh 128kb block904 0388h 0000h~00ffh 128kb block936 03a8h 0000h~00ffh 128kb block905 0389h 0000h~00ffh 128kb block937 03a9h 0000h~00ffh 128kb block906 038ah 0000h~00ffh 128kb block938 03aah 0000h~00ffh 128kb block907 038bh 0000h~00ffh 128kb block939 03abh 0000h~00ffh 128kb block908 038ch 0000h~00ffh 128kb block940 03ach 0000h~00ffh 128kb block909 038dh 0000h~00ffh 128kb block941 03adh 0000h~00ffh 128kb block910 038eh 0000h~00ffh 128kb block942 03aeh 0000h~00ffh 128kb block911 038fh 0000h~00ffh 128kb block943 03afh 0000h~00ffh 128kb block912 0390h 0000h~00ffh 128kb block944 03b0h 0000h~00ffh 128kb block913 0391h 0000h~00ffh 128kb block945 03b1h 0000h~00ffh 128kb block914 0392h 0000h~00ffh 128kb block946 03b2h 0000h~00ffh 128kb block915 0393h 0000h~00ffh 128kb block947 03b3h 0000h~00ffh 128kb block916 0394h 0000h~00ffh 128kb block948 03b4h 0000h~00ffh 128kb block917 0395h 0000h~00ffh 128kb block949 03b5h 0000h~00ffh 128kb block918 0396h 0000h~00ffh 128kb block950 03b6h 0000h~00ffh 128kb block919 0397h 0000h~00ffh 128kb block951 03b7h 0000h~00ffh 128kb block920 0398h 0000h~00ffh 128kb block952 03b8h 0000h~00ffh 128kb block921 0399h 0000h~00ffh 128kb block953 03b9h 0000h~00ffh 128kb block922 039ah 0000h~00ffh 128kb block954 03bah 0000h~00ffh 128kb block923 039bh 0000h~00ffh 128kb block955 03bbh 0000h~00ffh 128kb block924 039ch 0000h~00ffh 128kb block956 03bch 0000h~00ffh 128kb block925 039dh 0000h~00ffh 128kb block957 03bdh 0000h~00ffh 128kb block926 039eh 0000h~00ffh 128kb block958 03beh 0000h~00ffh 128kb block927 039fh 0000h~00ffh 128kb block959 03bfh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 32 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block960 03c0h 0000h~00ffh 128kb block992 03e0h 0000h~00ffh 128kb block961 03c1h 0000h~00ffh 128kb block993 03e1h 0000h~00ffh 128kb block962 03c2h 0000h~00ffh 128kb block994 03e2h 0000h~00ffh 128kb block963 03c3h 0000h~00ffh 128kb block995 03e3h 0000h~00ffh 128kb block964 03c4h 0000h~00ffh 128kb block996 03e4h 0000h~00ffh 128kb block965 03c5h 0000h~00ffh 128kb block997 03e5h 0000h~00ffh 128kb block966 03c6h 0000h~00ffh 128kb block998 03e6h 0000h~00ffh 128kb block967 03c7h 0000h~00ffh 128kb block999 03e7h 0000h~00ffh 128kb block968 03c8h 0000h~00ffh 128kb block1000 03e8h 0000h~00ffh 128kb block969 03c9h 0000h~00ffh 128kb block1001 03e9h 0000h~00ffh 128kb block970 03cah 0000h~00ffh 128kb block1002 03eah 0000h~00ffh 128kb block971 03cbh 0000h~00ffh 128kb block1003 03ebh 0000h~00ffh 128kb block972 03cch 0000h~00ffh 128kb block1004 03ech 0000h~00ffh 128kb block973 03cdh 0000h~00ffh 128kb block1005 03edh 0000h~00ffh 128kb block974 03ceh 0000h~00ffh 128kb block1006 03eeh 0000h~00ffh 128kb block975 03cfh 0000h~00ffh 128kb block1007 03efh 0000h~00ffh 128kb block976 03d0h 0000h~00ffh 128kb block1008 03f0h 0000h~00ffh 128kb block977 03d1h 0000h~00ffh 128kb block1009 03f1h 0000h~00ffh 128kb block978 03d2h 0000h~00ffh 128kb block1010 03f2h 0000h~00ffh 128kb block979 03d3h 0000h~00ffh 128kb block1011 03f3h 0000h~00ffh 128kb block980 03d4h 0000h~00ffh 128kb block1012 03f4h 0000h~00ffh 128kb block981 03d5h 0000h~00ffh 128kb block1013 03f5h 0000h~00ffh 128kb block982 03d6h 0000h~00ffh 128kb block1014 03f6h 0000h~00ffh 128kb block983 03d7h 0000h~00ffh 128kb block1015 03f7h 0000h~00ffh 128kb block984 03d8h 0000h~00ffh 128kb block1016 03f8h 0000h~00ffh 128kb block985 03d9h 0000h~00ffh 128kb block1017 03f9h 0000h~00ffh 128kb block986 03dah 0000h~00ffh 128kb block1018 03fah 0000h~00ffh 128kb block987 03dbh 0000h~00ffh 128kb block1019 03fbh 0000h~00ffh 128kb block988 03dch 0000h~00ffh 128kb block1020 03fch 0000h~00ffh 128kb block989 03ddh 0000h~00ffh 128kb block1021 03fdh 0000h~00ffh 128kb block990 03deh 0000h~00ffh 128kb block1022 03feh 0000h~00ffh 128kb block991 03dfh 0000h~00ffh 128kb block1023 03ffh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 33 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block1024 0400h 0000h~00ffh 128kb block1056 0420h 0000h~00ffh 128kb block1025 0401h 0000h~00ffh 128kb block1057 0421h 0000h~00ffh 128kb block1026 0402h 0000h~00ffh 128kb block1058 0422h 0000h~00ffh 128kb block1027 0403h 0000h~00ffh 128kb block1059 0423h 0000h~00ffh 128kb block1028 0404h 0000h~00ffh 128kb block1060 0424h 0000h~00ffh 128kb block1029 0405h 0000h~00ffh 128kb block1061 0425h 0000h~00ffh 128kb block1030 0406h 0000h~00ffh 128kb block1062 0426h 0000h~00ffh 128kb block1031 0407h 0000h~00ffh 128kb block1063 0427h 0000h~00ffh 128kb block1032 0408h 0000h~00ffh 128kb block1064 0428h 0000h~00ffh 128kb block1033 0409h 0000h~00ffh 128kb block1065 0429h 0000h~00ffh 128kb block1034 040ah 0000h~00ffh 128kb block1066 042ah 0000h~00ffh 128kb block1035 040bh 0000h~00ffh 128kb block1067 042bh 0000h~00ffh 128kb block1036 040ch 0000h~00ffh 128kb block1068 042ch 0000h~00ffh 128kb block1037 040dh 0000h~00ffh 128kb block1069 042dh 0000h~00ffh 128kb block1038 040eh 0000h~00ffh 128kb block1070 042eh 0000h~00ffh 128kb block1039 040fh 0000h~00ffh 128kb block1071 042fh 0000h~00ffh 128kb block1040 0410h 0000h~00ffh 128kb block1072 0430h 0000h~00ffh 128kb block1041 0411h 0000h~00ffh 128kb block1073 0431h 0000h~00ffh 128kb block1042 0412h 0000h~00ffh 128kb block1074 0432h 0000h~00ffh 128kb block1043 0413h 0000h~00ffh 128kb block1075 0433h 0000h~00ffh 128kb block1044 0414h 0000h~00ffh 128kb block1076 0434h 0000h~00ffh 128kb block1045 0415h 0000h~00ffh 128kb block1077 0435h 0000h~00ffh 128kb block1046 0416h 0000h~00ffh 128kb block1078 0436h 0000h~00ffh 128kb block1047 0417h 0000h~00ffh 128kb block1079 0437h 0000h~00ffh 128kb block1048 0418h 0000h~00ffh 128kb block1080 0438h 0000h~00ffh 128kb block1049 0419h 0000h~00ffh 128kb block1081 0439h 0000h~00ffh 128kb block1050 041ah 0000h~00ffh 128kb block1082 043ah 0000h~00ffh 128kb block1051 041bh 0000h~00ffh 128kb block1083 043bh 0000h~00ffh 128kb block1052 041ch 0000h~00ffh 128kb block1084 043ch 0000h~00ffh 128kb block1053 041dh 0000h~00ffh 128kb block1085 043dh 0000h~00ffh 128kb block1054 041eh 0000h~00ffh 128kb block1086 043eh 0000h~00ffh 128kb block1055 041fh 0000h~00ffh 128kb block1087 043fh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 34 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block1088 0440h 0000h~00ffh 128kb block1120 0460h 0000h~00ffh 128kb block1089 0441h 0000h~00ffh 128kb block1121 0461h 0000h~00ffh 128kb block1090 0442h 0000h~00ffh 128kb block1122 0462h 0000h~00ffh 128kb block1091 0443h 0000h~00ffh 128kb block1123 0463h 0000h~00ffh 128kb block1092 0444h 0000h~00ffh 128kb block1124 0464h 0000h~00ffh 128kb block1093 0445h 0000h~00ffh 128kb block1125 0465h 0000h~00ffh 128kb block1094 0446h 0000h~00ffh 128kb block1126 0466h 0000h~00ffh 128kb block1095 0447h 0000h~00ffh 128kb block1127 0467h 0000h~00ffh 128kb block1096 0448h 0000h~00ffh 128kb block1128 0468h 0000h~00ffh 128kb block1097 0449h 0000h~00ffh 128kb block1129 0469h 0000h~00ffh 128kb block1098 044ah 0000h~00ffh 128kb block1130 046ah 0000h~00ffh 128kb block1099 044bh 0000h~00ffh 128kb block1131 046bh 0000h~00ffh 128kb block1100 044ch 0000h~00ffh 128kb block1132 046ch 0000h~00ffh 128kb block1101 044dh 0000h~00ffh 128kb block1133 046dh 0000h~00ffh 128kb block1102 044eh 0000h~00ffh 128kb block1134 046eh 0000h~00ffh 128kb block1103 044fh 0000h~00ffh 128kb block1135 046fh 0000h~00ffh 128kb block1104 0450h 0000h~00ffh 128kb block1136 0470h 0000h~00ffh 128kb block1105 0451h 0000h~00ffh 128kb block1137 0471h 0000h~00ffh 128kb block1106 0452h 0000h~00ffh 128kb block1138 0472h 0000h~00ffh 128kb block1107 0453h 0000h~00ffh 128kb block1139 0473h 0000h~00ffh 128kb block1108 0454h 0000h~00ffh 128kb block1140 0474h 0000h~00ffh 128kb block1109 0455h 0000h~00ffh 128kb block1141 0475h 0000h~00ffh 128kb block1110 0456h 0000h~00ffh 128kb block1142 0476h 0000h~00ffh 128kb block1111 0457h 0000h~00ffh 128kb block1143 0477h 0000h~00ffh 128kb block1112 0458h 0000h~00ffh 128kb block1144 0478h 0000h~00ffh 128kb block1113 0459h 0000h~00ffh 128kb block1145 0479h 0000h~00ffh 128kb block1114 045ah 0000h~00ffh 128kb block1146 047ah 0000h~00ffh 128kb block1115 045bh 0000h~00ffh 128kb block1147 047bh 0000h~00ffh 128kb block1116 045ch 0000h~00ffh 128kb block1148 047ch 0000h~00ffh 128kb block1117 045dh 0000h~00ffh 128kb block1149 047dh 0000h~00ffh 128kb block1118 045eh 0000h~00ffh 128kb block1150 047eh 0000h~00ffh 128kb block1119 045fh 0000h~00ffh 128kb block1151 047fh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 35 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block1152 0480h 0000h~00ffh 128kb block1184 04a0h 0000h~00ffh 128kb block1153 0481h 0000h~00ffh 128kb block1185 04a1h 0000h~00ffh 128kb block1154 0482h 0000h~00ffh 128kb block1186 04a2h 0000h~00ffh 128kb block1155 0483h 0000h~00ffh 128kb block1187 04a3h 0000h~00ffh 128kb block1156 0484h 0000h~00ffh 128kb block1188 04a4h 0000h~00ffh 128kb block1157 0485h 0000h~00ffh 128kb block1189 04a5h 0000h~00ffh 128kb block1158 0486h 0000h~00ffh 128kb block1190 04a6h 0000h~00ffh 128kb block1159 0487h 0000h~00ffh 128kb block1191 04a7h 0000h~00ffh 128kb block1160 0488h 0000h~00ffh 128kb block1192 04a8h 0000h~00ffh 128kb block1161 0489h 0000h~00ffh 128kb block1193 04a9h 0000h~00ffh 128kb block1162 048ah 0000h~00ffh 128kb block1194 04aah 0000h~00ffh 128kb block1163 048bh 0000h~00ffh 128kb block1195 04abh 0000h~00ffh 128kb block1164 048ch 0000h~00ffh 128kb block1196 04ach 0000h~00ffh 128kb block1165 048dh 0000h~00ffh 128kb block1197 04adh 0000h~00ffh 128kb block1166 048eh 0000h~00ffh 128kb block1198 04aeh 0000h~00ffh 128kb block1167 048fh 0000h~00ffh 128kb block1199 04afh 0000h~00ffh 128kb block1168 0490h 0000h~00ffh 128kb block1200 04b0h 0000h~00ffh 128kb block1169 0491h 0000h~00ffh 128kb block1201 04b1h 0000h~00ffh 128kb block1170 0492h 0000h~00ffh 128kb block1202 04b2h 0000h~00ffh 128kb block1171 0493h 0000h~00ffh 128kb block1203 04b3h 0000h~00ffh 128kb block1172 0494h 0000h~00ffh 128kb block1204 04b4h 0000h~00ffh 128kb block1173 0495h 0000h~00ffh 128kb block1205 04b5h 0000h~00ffh 128kb block1174 0496h 0000h~00ffh 128kb block1206 04b6h 0000h~00ffh 128kb block1175 0497h 0000h~00ffh 128kb block1207 04b7h 0000h~00ffh 128kb block1176 0498h 0000h~00ffh 128kb block1208 04b8h 0000h~00ffh 128kb block1177 0499h 0000h~00ffh 128kb block1209 04b9h 0000h~00ffh 128kb block1178 049ah 0000h~00ffh 128kb block1210 04bah 0000h~00ffh 128kb block1179 049bh 0000h~00ffh 128kb block1211 04bbh 0000h~00ffh 128kb block1180 049ch 0000h~00ffh 128kb block1212 04bch 0000h~00ffh 128kb block1181 049dh 0000h~00ffh 128kb block1213 04bdh 0000h~00ffh 128kb block1182 049eh 0000h~00ffh 128kb block1214 04beh 0000h~00ffh 128kb block1183 049fh 0000h~00ffh 128kb block1215 04bfh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 36 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block1216 04c0h 0000h~00ffh 128kb block1248 04e0h 0000h~00ffh 128kb block1217 04c1h 0000h~00ffh 128kb block1249 04e1h 0000h~00ffh 128kb block1218 04c2h 0000h~00ffh 128kb block1250 04e2h 0000h~00ffh 128kb block1219 04c3h 0000h~00ffh 128kb block1251 04e3h 0000h~00ffh 128kb block1220 04c4h 0000h~00ffh 128kb block1252 04e4h 0000h~00ffh 128kb block1221 04c5h 0000h~00ffh 128kb block1253 04e5h 0000h~00ffh 128kb block1222 04c6h 0000h~00ffh 128kb block1254 04e6h 0000h~00ffh 128kb block1223 04c7h 0000h~00ffh 128kb block1255 04e7h 0000h~00ffh 128kb block1224 04c8h 0000h~00ffh 128kb block1256 04e8h 0000h~00ffh 128kb block1225 04c9h 0000h~00ffh 128kb block1257 04e9h 0000h~00ffh 128kb block1226 04cah 0000h~00ffh 128kb block1258 04eah 0000h~00ffh 128kb block1227 04cbh 0000h~00ffh 128kb block1259 04ebh 0000h~00ffh 128kb block1228 04cch 0000h~00ffh 128kb block1260 04ech 0000h~00ffh 128kb block1229 04cdh 0000h~00ffh 128kb block1261 04edh 0000h~00ffh 128kb block1230 04ceh 0000h~00ffh 128kb block1262 04eeh 0000h~00ffh 128kb block1231 04cfh 0000h~00ffh 128kb block1263 04efh 0000h~00ffh 128kb block1232 04d0h 0000h~00ffh 128kb block1264 04f0h 0000h~00ffh 128kb block1233 04d1h 0000h~00ffh 128kb block1265 04f1h 0000h~00ffh 128kb block1234 04d2h 0000h~00ffh 128kb block1266 04f2h 0000h~00ffh 128kb block1235 04d3h 0000h~00ffh 128kb block1267 04f3h 0000h~00ffh 128kb block1236 04d4h 0000h~00ffh 128kb block1268 04f4h 0000h~00ffh 128kb block1237 04d5h 0000h~00ffh 128kb block1269 04f5h 0000h~00ffh 128kb block1238 04d6h 0000h~00ffh 128kb block1270 04f6h 0000h~00ffh 128kb block1239 04d7h 0000h~00ffh 128kb block1271 04f7h 0000h~00ffh 128kb block1240 04d8h 0000h~00ffh 128kb block1272 04f8h 0000h~00ffh 128kb block1241 04d9h 0000h~00ffh 128kb block1273 04f9h 0000h~00ffh 128kb block1242 04dah 0000h~00ffh 128kb block1274 04fah 0000h~00ffh 128kb block1243 04dbh 0000h~00ffh 128kb block1275 04fbh 0000h~00ffh 128kb block1244 04dch 0000h~00ffh 128kb block1276 04fch 0000h~00ffh 128kb block1245 04ddh 0000h~00ffh 128kb block1277 04fdh 0000h~00ffh 128kb block1246 04deh 0000h~00ffh 128kb block1278 04feh 0000h~00ffh 128kb block1247 04dfh 0000h~00ffh 128kb block1279 04ffh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 37 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block1280 0500h 0000h~00ffh 128kb block1312 0520h 0000h~00ffh 128kb block1281 0501h 0000h~00ffh 128kb block1313 0521h 0000h~00ffh 128kb block1282 0502h 0000h~00ffh 128kb block1314 0522h 0000h~00ffh 128kb block1283 0503h 0000h~00ffh 128kb block1315 0523h 0000h~00ffh 128kb block1284 0504h 0000h~00ffh 128kb block1316 0524h 0000h~00ffh 128kb block1285 0505h 0000h~00ffh 128kb block1317 0525h 0000h~00ffh 128kb block1286 0506h 0000h~00ffh 128kb block1318 0526h 0000h~00ffh 128kb block1287 0507h 0000h~00ffh 128kb block1319 0527h 0000h~00ffh 128kb block1288 0508h 0000h~00ffh 128kb block1320 0528h 0000h~00ffh 128kb block1289 0509h 0000h~00ffh 128kb block1321 0529h 0000h~00ffh 128kb block1290 050ah 0000h~00ffh 128kb block1322 052ah 0000h~00ffh 128kb block1291 050bh 0000h~00ffh 128kb block1323 052bh 0000h~00ffh 128kb block1292 050ch 0000h~00ffh 128kb block1324 052ch 0000h~00ffh 128kb block1293 050dh 0000h~00ffh 128kb block1325 052dh 0000h~00ffh 128kb block1294 050eh 0000h~00ffh 128kb block1326 052eh 0000h~00ffh 128kb block1295 050fh 0000h~00ffh 128kb block1327 052fh 0000h~00ffh 128kb block1296 0510h 0000h~00ffh 128kb block1328 0530h 0000h~00ffh 128kb block1297 0511h 0000h~00ffh 128kb block1329 0531h 0000h~00ffh 128kb block1298 0512h 0000h~00ffh 128kb block1330 0532h 0000h~00ffh 128kb block1299 0513h 0000h~00ffh 128kb block1331 0533h 0000h~00ffh 128kb block1300 0514h 0000h~00ffh 128kb block1332 0534h 0000h~00ffh 128kb block1301 0515h 0000h~00ffh 128kb block1333 0535h 0000h~00ffh 128kb block1302 0516h 0000h~00ffh 128kb block1334 0536h 0000h~00ffh 128kb block1303 0517h 0000h~00ffh 128kb block1335 0537h 0000h~00ffh 128kb block1304 0518h 0000h~00ffh 128kb block1336 0538h 0000h~00ffh 128kb block1305 0519h 0000h~00ffh 128kb block1337 0539h 0000h~00ffh 128kb block1306 051ah 0000h~00ffh 128kb block1338 053ah 0000h~00ffh 128kb block1307 051bh 0000h~00ffh 128kb block1339 053bh 0000h~00ffh 128kb block1308 051ch 0000h~00ffh 128kb block1340 053ch 0000h~00ffh 128kb block1309 051dh 0000h~00ffh 128kb block1341 053dh 0000h~00ffh 128kb block1310 051eh 0000h~00ffh 128kb block1342 053eh 0000h~00ffh 128kb block1311 051fh 0000h~00ffh 128kb block1343 053fh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 38 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block1344 0540h 0000h~00ffh 128kb block1376 0560h 0000h~00ffh 128kb block1345 0541h 0000h~00ffh 128kb block1377 0561h 0000h~00ffh 128kb block1346 0542h 0000h~00ffh 128kb block1378 0562h 0000h~00ffh 128kb block1347 0543h 0000h~00ffh 128kb block1379 0563h 0000h~00ffh 128kb block1348 0544h 0000h~00ffh 128kb block1380 0564h 0000h~00ffh 128kb block1349 0545h 0000h~00ffh 128kb block1381 0565h 0000h~00ffh 128kb block1350 0546h 0000h~00ffh 128kb block1382 0566h 0000h~00ffh 128kb block1351 0547h 0000h~00ffh 128kb block1383 0567h 0000h~00ffh 128kb block1352 0548h 0000h~00ffh 128kb block1384 0568h 0000h~00ffh 128kb block1353 0549h 0000h~00ffh 128kb block1385 0569h 0000h~00ffh 128kb block1354 054ah 0000h~00ffh 128kb block1386 056ah 0000h~00ffh 128kb block1355 054bh 0000h~00ffh 128kb block1387 056bh 0000h~00ffh 128kb block1356 054ch 0000h~00ffh 128kb block1388 056ch 0000h~00ffh 128kb block1357 054dh 0000h~00ffh 128kb block1389 056dh 0000h~00ffh 128kb block1358 054eh 0000h~00ffh 128kb block1390 056eh 0000h~00ffh 128kb block1359 054fh 0000h~00ffh 128kb block1391 056fh 0000h~00ffh 128kb block1360 0550h 0000h~00ffh 128kb block1392 0570h 0000h~00ffh 128kb block1361 0551h 0000h~00ffh 128kb block1393 0571h 0000h~00ffh 128kb block1362 0552h 0000h~00ffh 128kb block1394 0572h 0000h~00ffh 128kb block1363 0553h 0000h~00ffh 128kb block1395 0573h 0000h~00ffh 128kb block1364 0554h 0000h~00ffh 128kb block1396 0574h 0000h~00ffh 128kb block1365 0555h 0000h~00ffh 128kb block1397 0575h 0000h~00ffh 128kb block1366 0556h 0000h~00ffh 128kb block1398 0576h 0000h~00ffh 128kb block1367 0557h 0000h~00ffh 128kb block1399 0577h 0000h~00ffh 128kb block1368 0558h 0000h~00ffh 128kb block1400 0578h 0000h~00ffh 128kb block1369 0559h 0000h~00ffh 128kb block1401 0579h 0000h~00ffh 128kb block1370 055ah 0000h~00ffh 128kb block1402 057ah 0000h~00ffh 128kb block1371 055bh 0000h~00ffh 128kb block1403 057bh 0000h~00ffh 128kb block1372 055ch 0000h~00ffh 128kb block1404 057ch 0000h~00ffh 128kb block1373 055dh 0000h~00ffh 128kb block1405 057dh 0000h~00ffh 128kb block1374 055eh 0000h~00ffh 128kb block1406 057eh 0000h~00ffh 128kb block1375 055fh 0000h~00ffh 128kb block1407 057fh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 39 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block1408 0580h 0000h~00ffh 128kb block1440 05a0h 0000h~00ffh 128kb block1409 0581h 0000h~00ffh 128kb block1441 05a1h 0000h~00ffh 128kb block1410 0582h 0000h~00ffh 128kb block1442 05a2h 0000h~00ffh 128kb block1411 0583h 0000h~00ffh 128kb block1443 05a3h 0000h~00ffh 128kb block1412 0584h 0000h~00ffh 128kb block1444 05a4h 0000h~00ffh 128kb block1413 0585h 0000h~00ffh 128kb block1445 05a5h 0000h~00ffh 128kb block1414 0586h 0000h~00ffh 128kb block1446 05a6h 0000h~00ffh 128kb block1415 0587h 0000h~00ffh 128kb block1447 05a7h 0000h~00ffh 128kb block1416 0588h 0000h~00ffh 128kb block1448 05a8h 0000h~00ffh 128kb block1417 0589h 0000h~00ffh 128kb block1449 05a9h 0000h~00ffh 128kb block1418 058ah 0000h~00ffh 128kb block1450 05aah 0000h~00ffh 128kb block1419 058bh 0000h~00ffh 128kb block1451 05abh 0000h~00ffh 128kb block1420 058ch 0000h~00ffh 128kb block1452 05ach 0000h~00ffh 128kb block1421 058dh 0000h~00ffh 128kb block1453 05adh 0000h~00ffh 128kb block1422 058eh 0000h~00ffh 128kb block1454 05aeh 0000h~00ffh 128kb block1423 058fh 0000h~00ffh 128kb block1455 05afh 0000h~00ffh 128kb block1424 0590h 0000h~00ffh 128kb block1456 05b0h 0000h~00ffh 128kb block1425 0591h 0000h~00ffh 128kb block1457 05b1h 0000h~00ffh 128kb block1426 0592h 0000h~00ffh 128kb block1458 05b2h 0000h~00ffh 128kb block1427 0593h 0000h~00ffh 128kb block1459 05b3h 0000h~00ffh 128kb block1428 0594h 0000h~00ffh 128kb block1460 05b4h 0000h~00ffh 128kb block1429 0595h 0000h~00ffh 128kb block1461 05b5h 0000h~00ffh 128kb block1430 0596h 0000h~00ffh 128kb block1462 05b6h 0000h~00ffh 128kb block1431 0597h 0000h~00ffh 128kb block1463 05b7h 0000h~00ffh 128kb block1432 0598h 0000h~00ffh 128kb block1464 05b8h 0000h~00ffh 128kb block1433 0599h 0000h~00ffh 128kb block1465 05b9h 0000h~00ffh 128kb block1434 059ah 0000h~00ffh 128kb block1466 05bah 0000h~00ffh 128kb block1435 059bh 0000h~00ffh 128kb block1467 05bbh 0000h~00ffh 128kb block1436 059ch 0000h~00ffh 128kb block1468 05bch 0000h~00ffh 128kb block1437 059dh 0000h~00ffh 128kb block1469 05bdh 0000h~00ffh 128kb block1438 059eh 0000h~00ffh 128kb block1470 05beh 0000h~00ffh 128kb block1439 059fh 0000h~00ffh 128kb block1471 05bfh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 40 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block1472 05c0h 0000h~00ffh 128kb block1504 05e0h 0000h~00ffh 128kb block1473 05c1h 0000h~00ffh 128kb block1505 05e1h 0000h~00ffh 128kb block1474 05c2h 0000h~00ffh 128kb block1506 05e2h 0000h~00ffh 128kb block1475 05c3h 0000h~00ffh 128kb block1507 05e3h 0000h~00ffh 128kb block1476 05c4h 0000h~00ffh 128kb block1508 05e4h 0000h~00ffh 128kb block1477 05c5h 0000h~00ffh 128kb block1509 05e5h 0000h~00ffh 128kb block1478 05c6h 0000h~00ffh 128kb block1510 05e6h 0000h~00ffh 128kb block1479 05c7h 0000h~00ffh 128kb block1511 05e7h 0000h~00ffh 128kb block1480 05c8h 0000h~00ffh 128kb block1512 05e8h 0000h~00ffh 128kb block1481 05c9h 0000h~00ffh 128kb block1513 05e9h 0000h~00ffh 128kb block1482 05cah 0000h~00ffh 128kb block1514 05eah 0000h~00ffh 128kb block1483 05cbh 0000h~00ffh 128kb block1515 05ebh 0000h~00ffh 128kb block1484 05cch 0000h~00ffh 128kb block1516 05ech 0000h~00ffh 128kb block1485 05cdh 0000h~00ffh 128kb block1517 05edh 0000h~00ffh 128kb block1486 05ceh 0000h~00ffh 128kb block1518 05eeh 0000h~00ffh 128kb block1487 05cfh 0000h~00ffh 128kb block1519 05efh 0000h~00ffh 128kb block1488 05d0h 0000h~00ffh 128kb block1520 05f0h 0000h~00ffh 128kb block1489 05d1h 0000h~00ffh 128kb block1521 05f1h 0000h~00ffh 128kb block1490 05d2h 0000h~00ffh 128kb block1522 05f2h 0000h~00ffh 128kb block1491 05d3h 0000h~00ffh 128kb block1523 05f3h 0000h~00ffh 128kb block1492 05d4h 0000h~00ffh 128kb block1524 05f4h 0000h~00ffh 128kb block1493 05d5h 0000h~00ffh 128kb block1525 05f5h 0000h~00ffh 128kb block1494 05d6h 0000h~00ffh 128kb block1526 05f6h 0000h~00ffh 128kb block1495 05d7h 0000h~00ffh 128kb block1527 05f7h 0000h~00ffh 128kb block1496 05d8h 0000h~00ffh 128kb block1528 05f8h 0000h~00ffh 128kb block1497 05d9h 0000h~00ffh 128kb block1529 05f9h 0000h~00ffh 128kb block1498 05dah 0000h~00ffh 128kb block1530 05fah 0000h~00ffh 128kb block1499 05dbh 0000h~00ffh 128kb block1531 05fbh 0000h~00ffh 128kb block1500 05dch 0000h~00ffh 128kb block1532 05fch 0000h~00ffh 128kb block1501 05ddh 0000h~00ffh 128kb block1533 05fdh 0000h~00ffh 128kb block1502 05deh 0000h~00ffh 128kb block1534 05feh 0000h~00ffh 128kb block1503 05dfh 0000h~00ffh 128kb block1535 05ffh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 41 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block1536 0600h 0000h~00ffh 128kb block1568 0620h 0000h~00ffh 128kb block1537 0601h 0000h~00ffh 128kb block1569 0621h 0000h~00ffh 128kb block1538 0602h 0000h~00ffh 128kb block1570 0622h 0000h~00ffh 128kb block1539 0603h 0000h~00ffh 128kb block1571 0623h 0000h~00ffh 128kb block1540 0604h 0000h~00ffh 128kb block1572 0624h 0000h~00ffh 128kb block1541 0605h 0000h~00ffh 128kb block1573 0625h 0000h~00ffh 128kb block1542 0606h 0000h~00ffh 128kb block1574 0626h 0000h~00ffh 128kb block1543 0607h 0000h~00ffh 128kb block1575 0627h 0000h~00ffh 128kb block1544 0608h 0000h~00ffh 128kb block1576 0628h 0000h~00ffh 128kb block1545 0609h 0000h~00ffh 128kb block1577 0629h 0000h~00ffh 128kb block1546 060ah 0000h~00ffh 128kb block1578 062ah 0000h~00ffh 128kb block1547 060bh 0000h~00ffh 128kb block1579 062bh 0000h~00ffh 128kb block1548 060ch 0000h~00ffh 128kb block1580 062ch 0000h~00ffh 128kb block1549 060dh 0000h~00ffh 128kb block1581 062dh 0000h~00ffh 128kb block1550 060eh 0000h~00ffh 128kb block1582 062eh 0000h~00ffh 128kb block1551 060fh 0000h~00ffh 128kb block1583 062fh 0000h~00ffh 128kb block1552 0610h 0000h~00ffh 128kb block1584 0630h 0000h~00ffh 128kb block1553 0611h 0000h~00ffh 128kb block1585 0631h 0000h~00ffh 128kb block1554 0612h 0000h~00ffh 128kb block1586 0632h 0000h~00ffh 128kb block1555 0613h 0000h~00ffh 128kb block1587 0633h 0000h~00ffh 128kb block1556 0614h 0000h~00ffh 128kb block1588 0634h 0000h~00ffh 128kb block1557 0615h 0000h~00ffh 128kb block1589 0635h 0000h~00ffh 128kb block1558 0616h 0000h~00ffh 128kb block1590 0636h 0000h~00ffh 128kb block1559 0617h 0000h~00ffh 128kb block1591 0637h 0000h~00ffh 128kb block1560 0618h 0000h~00ffh 128kb block1592 0638h 0000h~00ffh 128kb block1561 0619h 0000h~00ffh 128kb block1593 0639h 0000h~00ffh 128kb block1562 061ah 0000h~00ffh 128kb block1594 063ah 0000h~00ffh 128kb block1563 061bh 0000h~00ffh 128kb block1595 063bh 0000h~00ffh 128kb block1564 061ch 0000h~00ffh 128kb block1596 063ch 0000h~00ffh 128kb block1565 061dh 0000h~00ffh 128kb block1597 063dh 0000h~00ffh 128kb block1566 061eh 0000h~00ffh 128kb block1598 063eh 0000h~00ffh 128kb block1567 061fh 0000h~00ffh 128kb block1599 063fh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 42 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block1600 0640h 0000h~00ffh 128kb block1632 0660h 0000h~00ffh 128kb block1601 0641h 0000h~00ffh 128kb block1633 0661h 0000h~00ffh 128kb block1602 0642h 0000h~00ffh 128kb block1634 0662h 0000h~00ffh 128kb block1603 0643h 0000h~00ffh 128kb block1635 0663h 0000h~00ffh 128kb block1604 0644h 0000h~00ffh 128kb block1636 0664h 0000h~00ffh 128kb block1605 0645h 0000h~00ffh 128kb block1637 0665h 0000h~00ffh 128kb block1606 0646h 0000h~00ffh 128kb block1638 0666h 0000h~00ffh 128kb block1607 0647h 0000h~00ffh 128kb block1639 0667h 0000h~00ffh 128kb block1608 0648h 0000h~00ffh 128kb block1640 0668h 0000h~00ffh 128kb block1609 0649h 0000h~00ffh 128kb block1641 0669h 0000h~00ffh 128kb block1610 064ah 0000h~00ffh 128kb block1642 066ah 0000h~00ffh 128kb block1611 064bh 0000h~00ffh 128kb block1643 066bh 0000h~00ffh 128kb block1612 064ch 0000h~00ffh 128kb block1644 066ch 0000h~00ffh 128kb block1613 064dh 0000h~00ffh 128kb block1645 066dh 0000h~00ffh 128kb block1614 064eh 0000h~00ffh 128kb block1646 066eh 0000h~00ffh 128kb block1615 064fh 0000h~00ffh 128kb block1647 066fh 0000h~00ffh 128kb block1616 0650h 0000h~00ffh 128kb block1648 0670h 0000h~00ffh 128kb block1617 0651h 0000h~00ffh 128kb block1649 0671h 0000h~00ffh 128kb block1618 0652h 0000h~00ffh 128kb block1650 0672h 0000h~00ffh 128kb block1619 0653h 0000h~00ffh 128kb block1651 0673h 0000h~00ffh 128kb block1620 0654h 0000h~00ffh 128kb block1652 0674h 0000h~00ffh 128kb block1621 0655h 0000h~00ffh 128kb block1653 0675h 0000h~00ffh 128kb block1622 0656h 0000h~00ffh 128kb block1654 0676h 0000h~00ffh 128kb block1623 0657h 0000h~00ffh 128kb block1655 0677h 0000h~00ffh 128kb block1624 0658h 0000h~00ffh 128kb block1656 0678h 0000h~00ffh 128kb block1625 0659h 0000h~00ffh 128kb block1657 0679h 0000h~00ffh 128kb block1626 065ah 0000h~00ffh 128kb block1658 067ah 0000h~00ffh 128kb block1627 065bh 0000h~00ffh 128kb block1659 067bh 0000h~00ffh 128kb block1628 065ch 0000h~00ffh 128kb block1660 067ch 0000h~00ffh 128kb block1629 065dh 0000h~00ffh 128kb block1661 067dh 0000h~00ffh 128kb block1630 065eh 0000h~00ffh 128kb block1662 067eh 0000h~00ffh 128kb block1631 065fh 0000h~00ffh 128kb block1663 067fh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 43 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block1664 0680h 0000h~00ffh 128kb block1696 06a0h 0000h~00ffh 128kb block1665 0681h 0000h~00ffh 128kb block1697 06a1h 0000h~00ffh 128kb block1666 0682h 0000h~00ffh 128kb block1698 06a2h 0000h~00ffh 128kb block1667 0683h 0000h~00ffh 128kb block1699 06a3h 0000h~00ffh 128kb block1668 0684h 0000h~00ffh 128kb block1700 06a4h 0000h~00ffh 128kb block1669 0685h 0000h~00ffh 128kb block1701 06a5h 0000h~00ffh 128kb block1670 0686h 0000h~00ffh 128kb block1702 06a6h 0000h~00ffh 128kb block1671 0687h 0000h~00ffh 128kb block1703 06a7h 0000h~00ffh 128kb block1672 0688h 0000h~00ffh 128kb block1704 06a8h 0000h~00ffh 128kb block1673 0689h 0000h~00ffh 128kb block1705 06a9h 0000h~00ffh 128kb block1674 068ah 0000h~00ffh 128kb block1706 06aah 0000h~00ffh 128kb block1675 068bh 0000h~00ffh 128kb block1707 06abh 0000h~00ffh 128kb block1676 068ch 0000h~00ffh 128kb block1708 06ach 0000h~00ffh 128kb block1677 068dh 0000h~00ffh 128kb block1709 06adh 0000h~00ffh 128kb block1678 068eh 0000h~00ffh 128kb block1710 06aeh 0000h~00ffh 128kb block1679 068fh 0000h~00ffh 128kb block1711 06afh 0000h~00ffh 128kb block1680 0690h 0000h~00ffh 128kb block1712 06b0h 0000h~00ffh 128kb block1681 0691h 0000h~00ffh 128kb block1713 06b1h 0000h~00ffh 128kb block1682 0692h 0000h~00ffh 128kb block1714 06b2h 0000h~00ffh 128kb block1683 0693h 0000h~00ffh 128kb block1715 06b3h 0000h~00ffh 128kb block1684 0694h 0000h~00ffh 128kb block1716 06b4h 0000h~00ffh 128kb block1685 0695h 0000h~00ffh 128kb block1717 06b5h 0000h~00ffh 128kb block1686 0696h 0000h~00ffh 128kb block1718 06b6h 0000h~00ffh 128kb block1687 0697h 0000h~00ffh 128kb block1719 06b7h 0000h~00ffh 128kb block1688 0698h 0000h~00ffh 128kb block1720 06b8h 0000h~00ffh 128kb block1689 0699h 0000h~00ffh 128kb block1721 06b9h 0000h~00ffh 128kb block1690 069ah 0000h~00ffh 128kb block1722 06bah 0000h~00ffh 128kb block1691 069bh 0000h~00ffh 128kb block1723 06bbh 0000h~00ffh 128kb block1692 069ch 0000h~00ffh 128kb block1724 06bch 0000h~00ffh 128kb block1693 069dh 0000h~00ffh 128kb block1725 06bdh 0000h~00ffh 128kb block1694 069eh 0000h~00ffh 128kb block1726 06beh 0000h~00ffh 128kb block1695 069fh 0000h~00ffh 128kb block1727 06bfh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 44 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block1728 06c0h 0000h~00ffh 128kb block1760 06e0h 0000h~00ffh 128kb block1729 06c1h 0000h~00ffh 128kb block1761 06e1h 0000h~00ffh 128kb block1730 06c2h 0000h~00ffh 128kb block1762 06e2h 0000h~00ffh 128kb block1731 06c3h 0000h~00ffh 128kb block1763 06e3h 0000h~00ffh 128kb block1732 06c4h 0000h~00ffh 128kb block1764 06e4h 0000h~00ffh 128kb block1733 06c5h 0000h~00ffh 128kb block1765 06e5h 0000h~00ffh 128kb block1734 06c6h 0000h~00ffh 128kb block1766 06e6h 0000h~00ffh 128kb block1735 06c7h 0000h~00ffh 128kb block1767 06e7h 0000h~00ffh 128kb block1736 06c8h 0000h~00ffh 128kb block1768 06e8h 0000h~00ffh 128kb block1737 06c9h 0000h~00ffh 128kb block1769 06e9h 0000h~00ffh 128kb block1738 06cah 0000h~00ffh 128kb block1770 06eah 0000h~00ffh 128kb block1739 06cbh 0000h~00ffh 128kb block1771 06ebh 0000h~00ffh 128kb block1740 06cch 0000h~00ffh 128kb block1772 06ech 0000h~00ffh 128kb block1741 06cdh 0000h~00ffh 128kb block1773 06edh 0000h~00ffh 128kb block1742 06ceh 0000h~00ffh 128kb block1774 06eeh 0000h~00ffh 128kb block1743 06cfh 0000h~00ffh 128kb block1775 06efh 0000h~00ffh 128kb block1744 06d0h 0000h~00ffh 128kb block1776 06f0h 0000h~00ffh 128kb block1745 06d1h 0000h~00ffh 128kb block1777 06f1h 0000h~00ffh 128kb block1746 06d2h 0000h~00ffh 128kb block1778 06f2h 0000h~00ffh 128kb block1747 06d3h 0000h~00ffh 128kb block1779 06f3h 0000h~00ffh 128kb block1748 06d4h 0000h~00ffh 128kb block1780 06f4h 0000h~00ffh 128kb block1749 06d5h 0000h~00ffh 128kb block1781 06f5h 0000h~00ffh 128kb block1750 06d6h 0000h~00ffh 128kb block1782 06f6h 0000h~00ffh 128kb block1751 06d7h 0000h~00ffh 128kb block1783 06f7h 0000h~00ffh 128kb block1752 06d8h 0000h~00ffh 128kb block1784 06f8h 0000h~00ffh 128kb block1753 06d9h 0000h~00ffh 128kb block1785 06f9h 0000h~00ffh 128kb block1754 06dah 0000h~00ffh 128kb block1786 06fah 0000h~00ffh 128kb block1755 06dbh 0000h~00ffh 128kb block1787 06fbh 0000h~00ffh 128kb block1756 06dch 0000h~00ffh 128kb block1788 06fch 0000h~00ffh 128kb block1757 06ddh 0000h~00ffh 128kb block1789 06fdh 0000h~00ffh 128kb block1758 06deh 0000h~00ffh 128kb block1790 06feh 0000h~00ffh 128kb block1759 06dfh 0000h~00ffh 128kb block1791 06ffh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 45 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block1792 0700h 0000h~00ffh 128kb block1824 0720h 0000h~00ffh 128kb block1793 0701h 0000h~00ffh 128kb block1825 0721h 0000h~00ffh 128kb block1794 0702h 0000h~00ffh 128kb block1826 0722h 0000h~00ffh 128kb block1795 0703h 0000h~00ffh 128kb block1827 0723h 0000h~00ffh 128kb block1796 0704h 0000h~00ffh 128kb block1828 0724h 0000h~00ffh 128kb block1797 0705h 0000h~00ffh 128kb block1829 0725h 0000h~00ffh 128kb block1798 0706h 0000h~00ffh 128kb block1830 0726h 0000h~00ffh 128kb block1799 0707h 0000h~00ffh 128kb block1831 0727h 0000h~00ffh 128kb block1800 0708h 0000h~00ffh 128kb block1832 0728h 0000h~00ffh 128kb block1801 0709h 0000h~00ffh 128kb block1833 0729h 0000h~00ffh 128kb block1802 070ah 0000h~00ffh 128kb block1834 072ah 0000h~00ffh 128kb block1803 070bh 0000h~00ffh 128kb block1835 072bh 0000h~00ffh 128kb block1804 070ch 0000h~00ffh 128kb block1836 072ch 0000h~00ffh 128kb block1805 070dh 0000h~00ffh 128kb block1837 072dh 0000h~00ffh 128kb block1806 070eh 0000h~00ffh 128kb block1838 072eh 0000h~00ffh 128kb block1807 070fh 0000h~00ffh 128kb block1839 072fh 0000h~00ffh 128kb block1808 0710h 0000h~00ffh 128kb block1840 0730h 0000h~00ffh 128kb block1809 0711h 0000h~00ffh 128kb block1841 0731h 0000h~00ffh 128kb block1810 0712h 0000h~00ffh 128kb block1842 0732h 0000h~00ffh 128kb block1811 0713h 0000h~00ffh 128kb block1843 0733h 0000h~00ffh 128kb block1812 0714h 0000h~00ffh 128kb block1844 0734h 0000h~00ffh 128kb block1813 0715h 0000h~00ffh 128kb block1845 0735h 0000h~00ffh 128kb block1814 0716h 0000h~00ffh 128kb block1846 0736h 0000h~00ffh 128kb block1815 0717h 0000h~00ffh 128kb block1847 0737h 0000h~00ffh 128kb block1816 0718h 0000h~00ffh 128kb block1848 0738h 0000h~00ffh 128kb block1817 0719h 0000h~00ffh 128kb block1849 0739h 0000h~00ffh 128kb block1818 071ah 0000h~00ffh 128kb block1850 073ah 0000h~00ffh 128kb block1819 071bh 0000h~00ffh 128kb block1851 073bh 0000h~00ffh 128kb block1820 071ch 0000h~00ffh 128kb block1852 073ch 0000h~00ffh 128kb block1821 071dh 0000h~00ffh 128kb block1853 073dh 0000h~00ffh 128kb block1822 071eh 0000h~00ffh 128kb block1854 073eh 0000h~00ffh 128kb block1823 071fh 0000h~00ffh 128kb block1855 073fh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 46 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block1856 0740h 0000h~00ffh 128kb block1888 0760h 0000h~00ffh 128kb block1857 0741h 0000h~00ffh 128kb block1889 0761h 0000h~00ffh 128kb block1858 0742h 0000h~00ffh 128kb block1890 0762h 0000h~00ffh 128kb block1859 0743h 0000h~00ffh 128kb block1891 0763h 0000h~00ffh 128kb block1860 0744h 0000h~00ffh 128kb block1892 0764h 0000h~00ffh 128kb block1861 0745h 0000h~00ffh 128kb block1893 0765h 0000h~00ffh 128kb block1862 0746h 0000h~00ffh 128kb block1894 0766h 0000h~00ffh 128kb block1863 0747h 0000h~00ffh 128kb block1895 0767h 0000h~00ffh 128kb block1864 0748h 0000h~00ffh 128kb block1896 0768h 0000h~00ffh 128kb block1865 0749h 0000h~00ffh 128kb block1897 0769h 0000h~00ffh 128kb block1866 074ah 0000h~00ffh 128kb block1898 076ah 0000h~00ffh 128kb block1867 074bh 0000h~00ffh 128kb block1899 076bh 0000h~00ffh 128kb block1868 074ch 0000h~00ffh 128kb block1900 076ch 0000h~00ffh 128kb block1869 074dh 0000h~00ffh 128kb block1901 076dh 0000h~00ffh 128kb block1870 074eh 0000h~00ffh 128kb block1902 076eh 0000h~00ffh 128kb block1871 074fh 0000h~00ffh 128kb block1903 076fh 0000h~00ffh 128kb block1872 0750h 0000h~00ffh 128kb block1904 0770h 0000h~00ffh 128kb block1873 0751h 0000h~00ffh 128kb block1905 0771h 0000h~00ffh 128kb block1874 0752h 0000h~00ffh 128kb block1906 0772h 0000h~00ffh 128kb block1875 0753h 0000h~00ffh 128kb block1907 0773h 0000h~00ffh 128kb block1876 0754h 0000h~00ffh 128kb block1908 0774h 0000h~00ffh 128kb block1877 0755h 0000h~00ffh 128kb block1909 0775h 0000h~00ffh 128kb block1878 0756h 0000h~00ffh 128kb block1910 0776h 0000h~00ffh 128kb block1879 0757h 0000h~00ffh 128kb block1911 0777h 0000h~00ffh 128kb block1880 0758h 0000h~00ffh 128kb block1912 0778h 0000h~00ffh 128kb block1881 0759h 0000h~00ffh 128kb block1913 0779h 0000h~00ffh 128kb block1882 075ah 0000h~00ffh 128kb block1914 077ah 0000h~00ffh 128kb block1883 075bh 0000h~00ffh 128kb block1915 077bh 0000h~00ffh 128kb block1884 075ch 0000h~00ffh 128kb block1916 077ch 0000h~00ffh 128kb block1885 075dh 0000h~00ffh 128kb block1917 077dh 0000h~00ffh 128kb block1886 075eh 0000h~00ffh 128kb block1918 077eh 0000h~00ffh 128kb block1887 075fh 0000h~00ffh 128kb block1919 077fh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 47 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block1920 0780h 0000h~00ffh 128kb block1952 07a0h 0000h~00ffh 128kb block1921 0781h 0000h~00ffh 128kb block1953 07a1h 0000h~00ffh 128kb block1922 0782h 0000h~00ffh 128kb block1954 07a2h 0000h~00ffh 128kb block1923 0783h 0000h~00ffh 128kb block1955 07a3h 0000h~00ffh 128kb block1924 0784h 0000h~00ffh 128kb block1956 07a4h 0000h~00ffh 128kb block1925 0785h 0000h~00ffh 128kb block1957 07a5h 0000h~00ffh 128kb block1926 0786h 0000h~00ffh 128kb block1958 07a6h 0000h~00ffh 128kb block1927 0787h 0000h~00ffh 128kb block1959 07a7h 0000h~00ffh 128kb block1928 0788h 0000h~00ffh 128kb block1960 07a8h 0000h~00ffh 128kb block1929 0789h 0000h~00ffh 128kb block1961 07a9h 0000h~00ffh 128kb block1930 078ah 0000h~00ffh 128kb block1962 07aah 0000h~00ffh 128kb block1931 078bh 0000h~00ffh 128kb block1963 07abh 0000h~00ffh 128kb block1932 078ch 0000h~00ffh 128kb block1964 07ach 0000h~00ffh 128kb block1933 078dh 0000h~00ffh 128kb block1965 07adh 0000h~00ffh 128kb block1934 078eh 0000h~00ffh 128kb block1966 07aeh 0000h~00ffh 128kb block1935 078fh 0000h~00ffh 128kb block1967 07afh 0000h~00ffh 128kb block1936 0790h 0000h~00ffh 128kb block1968 07b0h 0000h~00ffh 128kb block1937 0791h 0000h~00ffh 128kb block1969 07b1h 0000h~00ffh 128kb block1938 0792h 0000h~00ffh 128kb block1970 07b2h 0000h~00ffh 128kb block1939 0793h 0000h~00ffh 128kb block1971 07b3h 0000h~00ffh 128kb block1940 0794h 0000h~00ffh 128kb block1972 07b4h 0000h~00ffh 128kb block1941 0795h 0000h~00ffh 128kb block1973 07b5h 0000h~00ffh 128kb block1942 0796h 0000h~00ffh 128kb block1974 07b6h 0000h~00ffh 128kb block1943 0797h 0000h~00ffh 128kb block1975 07b7h 0000h~00ffh 128kb block1944 0798h 0000h~00ffh 128kb block1976 07b8h 0000h~00ffh 128kb block1945 0799h 0000h~00ffh 128kb block1977 07b9h 0000h~00ffh 128kb block1946 079ah 0000h~00ffh 128kb block1978 07bah 0000h~00ffh 128kb block1947 079bh 0000h~00ffh 128kb block1979 07bbh 0000h~00ffh 128kb block1948 079ch 0000h~00ffh 128kb block1980 07bch 0000h~00ffh 128kb block1949 079dh 0000h~00ffh 128kb block1981 07bdh 0000h~00ffh 128kb block1950 079eh 0000h~00ffh 128kb block1982 07beh 0000h~00ffh 128kb block1951 079fh 0000h~00ffh 128kb block1983 07bfh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 48 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) block block address page and sector address size block block address page and sector address size block1984 07c0h 0000h~00ffh 128kb block2016 07e0h 0000h~00ffh 128kb block1985 07c1h 0000h~00ffh 128kb block2017 07e1h 0000h~00ffh 128kb block1986 07c2h 0000h~00ffh 128kb block2018 07e2h 0000h~00ffh 128kb block1987 07c3h 0000h~00ffh 128kb block2019 07e3h 0000h~00ffh 128kb block1988 07c4h 0000h~00ffh 128kb block2020 07e4h 0000h~00ffh 128kb block1989 07c85h 0000h~00ffh 128kb block2021 07e5h 0000h~00ffh 128kb block1990 07c6h 0000h~00ffh 128kb block2022 07e6h 0000h~00ffh 128kb block1991 07c7h 0000h~00ffh 128kb block2023 07e7h 0000h~00ffh 128kb block1992 07c8h 0000h~00ffh 128kb block2024 07e8h 0000h~00ffh 128kb block1993 07c9h 0000h~00ffh 128kb block2025 07e9h 0000h~00ffh 128kb block1994 07cah 0000h~00ffh 128kb block2026 07eah 0000h~00ffh 128kb block1995 07cbh 0000h~00ffh 128kb block2027 07ebh 0000h~00ffh 128kb block1996 07cch 0000h~00ffh 128kb block2028 07ech 0000h~00ffh 128kb block1997 07cdh 0000h~00ffh 128kb block2029 07edh 0000h~00ffh 128kb block1998 07ceh 0000h~00ffh 128kb block2030 07eeh 0000h~00ffh 128kb block1999 07cfh 0000h~00ffh 128kb block2031 07efh 0000h~00ffh 128kb block2000 07d0h 0000h~00ffh 128kb block2032 07f0h 0000h~00ffh 128kb block2001 07d1h 0000h~00ffh 128kb block2033 07f1h 0000h~00ffh 128kb block2002 07d2h 0000h~00ffh 128kb block2034 07f2h 0000h~00ffh 128kb block2003 07d3h 0000h~00ffh 128kb block2035 07f3h 0000h~00ffh 128kb block2004 07d4h 0000h~00ffh 128kb block2036 07f4h 0000h~00ffh 128kb block2005 07d5h 0000h~00ffh 128kb block2037 07f5h 0000h~00ffh 128kb block2006 07d6h 0000h~00ffh 128kb block2038 07f6h 0000h~00ffh 128kb block2007 07d7h 0000h~00ffh 128kb block2039 07f7h 0000h~00ffh 128kb block2008 07d8h 0000h~00ffh 128kb block2040 07f8h 0000h~00ffh 128kb block2009 07d9h 0000h~00ffh 128kb block2041 07f9h 0000h~00ffh 128kb block2010 07dah 0000h~00ffh 128kb block2042 07fah 0000h~00ffh 128kb block2011 07dbh 0000h~00ffh 128kb block2043 07fbh 0000h~00ffh 128kb block2012 07dch 0000h~00ffh 128kb block2044 07fch 0000h~00ffh 128kb block2013 07ddh 0000h~00ffh 128kb block2045 07fdh 0000h~00ffh 128kb block2014 07deh 0000h~00ffh 128kb block2046 07feh 0000h~00ffh 128kb block2015 07dfh 0000h~00ffh 128kb block2047 07ffh 0000h~00ffh 128kb
onenand2g(kfg2g16q2m-debx) flash memory 49 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the figure below shows the assignment of the spare area in the internal memory nand array. main area 256w main area 256w main area 256w main area 256w spare area 8w spare area 8w spare area 8w spare area 8w ^ 1 st w eccm 1st eccm 2nd eccm 3rd eccs 1st eccs 2nd lsb msb lsb msb ^ 2 nd w lsb msb ^ 3 rd w lsb msb ^ 4 th w lsb msb ^ 5 th w lsb msb ^ 6 th w lsb msb ^ 7 th w lsb msb ^ 8 th w lsb msb note1 note1 note2 note2 note2 note3 note3 note3 note4 note4 note3 2.7.2 internal memory spare area assignment spare area assignment in the internal memory nand array information note 5 : for all blocks, 8th word is available to the user. however,in case of otp block, 8th word of sector 0, page 0 is reserved as otp locking bit area. therefore, in case of otp block, user usage on this area is prohibited. word byte note description 1 lsb 1 invalid block information in 1st and 2nd page of an invalid block msb 2 lsb 2 managed by internal ecc logic for logical sector number data msb 3 lsb msb 3 reserved for future use 4 lsb msb 5 lsb dedicated to internal ecc logic. read only. eccm 1st for main area data msb dedicated to internal ecc logic. read only. eccm 2nd for main area data 6 lsb dedicated to internal ecc logic. read only. eccm 3rd for main area data msb dedicated to internal ecc logic. read only. eccs 1st for 2nd word of spare area data 7 lsb dedicated to internal ecc logic. read only. eccs 2nd for 3rd word of spare area data msb 3 reserved for future use 8 lsb 4 available to the user (note 5) msb
onenand2g(kfg2g16q2m-debx) flash memory 50 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) division address (word order) address (byte order) size (total 128kb) usage description main area (64kb) 0000h~00ffh 00000h~001feh 512b 1kb r bootm 0 bootram main sector0 0100h~01ffh 00200h~003feh 512b bootm 1 bootram main sector1 0200h~02ffh 00400h~005feh 512b 4kb r/w datam 0_0 dataram main page0/sector0 0300h~03ffh 00600h~007feh 512b datam 0_1 dataram main page0/sector1 0400h~04ffh 00800h~009feh 512b datam 0_2 dataram main page0/sector2 0500h~05ffh 00a00h~00bfeh 512b datam 0_3 dataram main page0/sector3 0600h~06ffh 00c00h~00dfeh 512b datam 1_0 dataram main page1/sector0 0700h~07ffh 00e00h~00ffeh 512b datam 1_1 dataram main page1/sector1 0800h~08ffh 01000h~011feh 512b datam 1_2 dataram main page1/sector2 0900h~09ffh 01200h~013feh 512b datam 1_3 dataram main page1/sector3 0a00h~7fffh 01400h~0fffeh 59k 59k - reserved reserved spare area (8kb) 8000h~8007h 10000h~1000eh 16b 32b r boots 0 bootram spare sector0 8008h~800fh 10010h~1001eh 16b boots 1 bootram spare sector1 8010h~8017h 10020h~1002eh 16b 128b r/w datas 0_0 dataram spare page0/sector0 8018h~801fh 10030h~1003eh 16b datas 0_1 dataram spare page0/sector1 8020h~8027h 10040h~1004eh 16b datas 0_2 dataram spare page0/sector2 8028h~802fh 10050h~1005eh 16b datas 0_3 dataram spare page0/sector3 8030h~8037h 10060h~1006eh 16b datas 1_0 dataram spare page1/sector0 8038h~803fh 10070h~1007eh 16b datas 1_1 dataram spare page1/sector1 8040h~8047h 10080h~1008eh 16b datas 1_2 dataram spare page1/sector2 8048h~804fh 10090h~1009eh 16b datas 1_3 dataram spare page1/sector3 8050h~8fffh 100a0h~11ffeh 8032b 8032b - reserved reserved reserved (24kb) 9000h~bfffh 12000h~17ffeh 24kb 24kb - reserved reserved reserved (8kb) c000h~cfffh 18000h~19ffeh 8kb 8kb - reserved reserved reserved (16kb) d000h~efffh 1a000h~1dffeh 16kb 16kb - reserved reserved registers (8kb) f000h~ffffh 1e000h~1fffeh 8kb 8kb r or r/w registers registers the following table shows the external memory address map in word and byte order. note that the data output is unknown while host reads a register bit of reserved area. 2.7.3 external memory (bufferram) address map
onenand2g(kfg2g16q2m-debx) flash memory 51 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the tables below show word order address map information for the bootram and dataram main and spare areas. -0000h~01ffh: 2(sector) x 512byte(nand main area) = 1kb 0000h~00ffh(512b) bootm 0 (sector 0 of page 0) 0100h~01ffh(512b) bootm 1 (sector 1 of page 0) x bootram(main area) -0200h~09ffh: 8(sector) x 512byte(nand main area) = 4kb 0200h~02ffh(512b) datam 0_0 (sector 0 of page 0) 0300h~03ffh(512b) datam 0_1 (sector 1 of page 0) 0400h~04ffh(512b) datam 0_2 (sector 2 of page 0) 0500h~05ffh(512b) datam 0_3 (sector 3 of page 0) 0600h~06ffh(512b) datam 1_0 (sector 0 of page 1) 0700h~07ffh(512b) datam 1_1 (sector 1 of page 1) 0800h~08ffh(512b) datam 1_2 (sector 2 of page 1) 0900h~09ffh(512b) datam 1_3 (sector 3 of page 1) x dataram(main area) -8000h~800fh: 2(sector) x 16byte(nand spare area) = 32b 8000h~8007h(16b) boots 0 (sector 0 of page 0) 8008h~800fh(16b) boots 1 (sector 1 of page 0) x bootram(spare area) -8010h~804fh: 8(sector) x 16byte(nand spare area) = 128b *nand flash array consists of 2kb page size and 128kb block size. 8010h~8017h(16b) datas 0_0 (sector 0 of page 0) 8018h~801fh(16b) datas 0_1 (sector 1 of page 0) 8020h~8027h(16b) datas 0_2 (sector 2 of page 0) 8028h~802fh(16b) datas 0_3 (sector 3 of page 0) 8030h~8037h(16b) datas 1_0 (sector 0 of page 1) 8038h~803fh(16b) datas 1_1 (sector 1 of page 1) 8040h~8047h(16b) datas 1_2 (sector 2 of page 1) 8048h~804fh(16b) datas 1_3 (sector 3 of page 1) x dataram(spare area) 2.7.4 external memory map detail information
onenand2g(kfg2g16q2m-debx) flash memory 52 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) buf. word address byte address f e d c b a 9 8 7 6 5 4 3 2 1 0 boots 0 8000h 10000h bi 8001h 10002h managed by internal ecc logic 8002h 10004h reserved for the future use managed by internal ecc logic 8003h 10006h reserved for the current and future use 8004h 10008h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 8005h 1000ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 8006h 1000ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 8007h 1000eh free usage boots 1 8008h 10010h bi 8009h 10012h managed by internal ecc logic 800ah 10014h reserved for the future use managed by internal ecc logic 800bh 10016h reserved for the current and future use 800ch 10018h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 800dh 1001ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 800eh 1001ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 800fh 1001eh free usage datas 0_0 8010h 10020h bi 8011h 10022h managed by internal ecc logic 8012h 10024h reserved for the future use managed by internal ecc logic 8013h 10026h reserved for the current and future use 8014h 10028h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 8015h 1002ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 8016h 1002ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 8017h 1002eh free usage datas 0_1 8018h 10030h bi 8019h 10032h managed by internal ecc logic 801ah 10034h reserved for the future use managed by internal ecc logic 801bh 10036h reserved for the current and future use 801ch 10038h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 801dh 1003ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 801eh 1003ch ffh(reserved for the future use) ecc code for spare area data (2 nd ) 801fh 1003eh free usage equivalent to 1word of nand flash 2.7.5 external memory spare area assignment
onenand2g(kfg2g16q2m-debx) flash memory 53 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) buf. word address byte address f e d c b a 9 8 7 6 5 4 3 2 1 0 datas 0_2 8020h 10040h bi 8021h 10042h managed by internal ecc logic 8022h 10044h reserved for the future use managed by internal ecc logic 8023h 10046h reserved for the current and future use 8024h 10048h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 8025h 1004ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 8026h 1004ch reserved for the future use ecc code for spare area data (2 nd ) 8027h 1004eh free usage datas 0_3 8028h 10050h bi 8029h 10052h managed by internal ecc logic 802ah 10054h reserved for the future use managed by internal ecc logic 802bh 10056h reserved for the current and future use 802ch 10058h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 802dh 1005ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 802eh 1005ch reserved for the future use ecc code for spare area data (2 nd ) 802fh 1005eh free usage datas 1_0 8030h 10060h bi 8031h 10062h managed by internal ecc logic 8032h 10064h reserved for the future use managed by internal ecc logic 8033h 10066h reserved for the current and future use 8034h 10068h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 8035h 1006ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 8036h 1006ch reserved for the future use ecc code for spare area data (2 nd ) 8037h 1006eh free usage datas 1_1 8038h 10070h bi 8039h 10072h managed by internal ecc logic 803ah 10074h reserved for the future use managed by internal ecc logic 803bh 10076h reserved for the current and future use 803ch 10078h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 803dh 1007ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 803eh 1007ch reserved for the future use ecc code for spare area data (2 nd ) 803fh 1007eh free usage datas 1_2 8040h 10080h bi 8041h 10082h managed by internal ecc logic 8042h 10084h reserved for the future use managed by internal ecc logic 8043h 10086h reserved for the current and future use 8044h 10088h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 8045h 1008ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 8046h 1008ch reserved for the future use ecc code for spare area data (2 nd ) 8047h 1008eh free usage
onenand2g(kfg2g16q2m-debx) flash memory 54 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) equivalent to 1word of nand flash note: - bi: bad block information >host can use complete spare area except bi and ecc code area. for example, host can write data to spare area buffer except for the area controlled by ecc logic at program operation. >in case of with ecc mode, onenand automatically generates ecc code for both main and spare data of memory during program ope ration, but does not update ecc code to spare bufferram during load operation. >when loading/programming spare area, spare area bufferram address(bsa) and bufferram sector count(bsc) is chosen via start bu ffer register as it is. buf. word address byte address f e d c b a 9 8 7 6 5 4 3 2 1 0 datas 1_3 8048h 10090h bi 8049h 10092h managed by internal ecc logic 804ah 10094h reserved for the future use managed by internal ecc logic 804bh 10096h reserved for the current and future use 804ch 10098h ecc code for main area data (2 nd ) ecc code for main area data (1 st ) 804dh 1009ah ecc code for spare area data (1 st ) ecc code for main area data (3 rd ) 804eh 1009ch reserved for the future use ecc code for spare area data (2 nd ) 804fh 1009eh free usage equivalent to 1word of nand flash
onenand2g(kfg2g16q2m-debx) flash memory 55 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) section 2.8 of this specification provides information about the onenand2g registers. 2.8.1 register address map this map describes the register addresses, register name, register description, and host accessibility. address (word order) address (byte order) name host access description f000h 1e000h manufacturer id r manufacturer identification f001h 1e002h device id r device identification f002h 1e004h version id r n/a f003h 1e006h data buffer size r data buffer size f004h 1e008h boot buffer size r boot buffer size f005h 1e00ah amount of buffers r amount of data/boot buffers f006h 1e00ch technology r info about technology f007h~f0ffh 1e00eh~1e1feh reserved - reserved for user f100h 1e200h start address 1 r/w chip address for selection of nand core in ddp & block address f101h 1e202h start address 2 r/w chip address for selection of bufferram in ddp f102h 1e204h start address 3 r/w destination block address for copy back program f103h 1e206h start address 4 r/w destination page & sector address for copy back program f104h 1e208h start address 5 r/w number of page in synchronous burst block read f105h 1e20ah start address 6 - n/a f106h 1e20ch start address 7 - n/a f107h 1e20eh start address 8 r/w nand flash page & sector address f108h~f1ffh 1e210h~1e3feh reserved - reserved for user f200h 1e400h start buffer r/w buffer number for the page data transfer to/from the memory and the start buffer address the meaning is with which buffer to start and how many buffers to use for the data transfer f201h~f207h 1e402h~1e40eh reserved - reserved for user f208h~f21fh 1e410h~1e43eh reserved - reserved for vendor specific purposes f220h 1e440h command r/w host control and memory operation commands f221h 1e442h system configuration 1 r, r/w memory and host interface configuration f222h 1e444h system configuration 2 -n/a f223h~f22fh 1e446h~1e45eh reserved - reserved for user f230h~f23fh 1e460h~1e47eh reserved - reserved for vendor specific purposes f240h 1e480h controller status r controller status and result of memory operation f241h 1e482h interrupt r/w memory command completion interrupt status f242h~f24bh 1e484h~1e496h reserved - reserved for user f24ch 1e498h start block address r/w start memory block address in write protection mode 2.8 registers
onenand2g(kfg2g16q2m-debx) flash memory 56 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) address (word order) address (byte order) name host access description f24dh 1e49ah reserved - reserved for user f24eh 1e49ch write protection status r current memory write protection status (unlocked/locked/tight-locked) f24fh~feffh 1e49eh~1fdfeh reserved - reserved for user ff00h 1fe00h ecc status register r ecc status of sector ff01h 1fe02h ecc result of main area data r ecc error position of main area data error for first selected sector ff02h 1fe04h ecc result of spare area data r ecc error position of spare area data error for first selected sector ff03h 1fe06h ecc result of main area data r ecc error position of main area data error for second selected sector ff04h 1fe08h ecc result of spare area data r ecc error position of spare area data error for second selected sector ff05h 1fe0ah ecc result of main area data r ecc error position of main area data error for third selected sector ff06h 1fe0ch ecc result of spare area data r ecc error position of spare area data error for third selected sector ff07h 1fe0eh ecc result of main area data r ecc error position of main area data error for fourth selected sector ff08h 1fe10h ecc result of spare area data r ecc error position of spare area data error for fourth selected sector ff09h~ffffh 1fe12h~1fffeh reserved - reserved for vendor specific purposes this read register describes the manufacturer's identification. samsung electronics company manufacturer's id is 00ech. f000h, default = 00ech 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 manufid 2.8.2 manufacturer id register f000h (r)
onenand2g(kfg2g16q2m-debx) flash memory 57 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) this read register describes the device. f001h, see table for default. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 deviceid device identification device id default note1) due to kfw8g16q2m is qdp with dual KFH4G16Q2M, device id[15:0] is same as KFH4G16Q2M register information description deviceid [1:0] vcc 00 = 1.8v, 01/10/11 = reserved deviceid [2] muxed/demuxed 0 = muxed, 1 = demuxed deviceid [3] single/ddp 0 = single, 1 = ddp deviceid [7:4] density 0000 = 128mb, 0001 = 256mb, 0010 = 512mb, 0011 = 1gb, 0100 = 2gb, 0101=4gb deviceid [8] bottom boot 0 = bottom boot device deviceid[15:0] kfg2g16q2m 0044h KFH4G16Q2M 005ch kfw8g16q2m 005ch 2.8.3 device id register f001h (r)
onenand2g(kfg2g16q2m-debx) flash memory 58 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 2.8.5 data buffer size register f003h (r) this read register describes the size of the data buffer. f003h, default = 0800h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 databufsize data buffer size information register information description databufsize total data buffer size in words equal to 2 buffers of 1024 words each (2 x 1024 = 2 11 ) in the memory interface 2.8.4 version id register f002h this register is reserved for future use.
onenand2g(kfg2g16q2m-debx) flash memory 59 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 2.8.7 number of buffers register f005h (r) this read register describes the number of each buffer. f005h, default = 0201h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 databufamount bootbufamount number of buffers information register information description databufamount the number of data buffers = 2 (2 n , n=1) bootbufamount the number of boot buffers = 1 (2 n , n=0) 2.8.8 technology register f006h (r) this read register describes the internal nand array technology. f006h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 te c h technology information technology register setting nand slc 0000h nand mlc 0001h reserved 0002h ~ ffffh this read register describes the size of the boot buffer. f004h, default = 0200h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bootbufsize register information description bootbufsize total boot buffer size in words equal to 1 buffer of 512 words (1 x 512 = 2 9 ) in the memory interface 2.8.6 boot buffer size register f004h (r)
onenand2g(kfg2g16q2m-debx) flash memory 60 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) device number of block fba 2gb 2048 fba[10:0] 4gb ddp 4096 dfs[15] & fba[10:0] start address1 information register information description fba nand flash block address dfs flash core of ddp (device flash core select) 2.8.10 start address2 register f101h (r/w) this read/write register describes the bufferram of ddp (device bufferram select) f101h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dbs reserved(000000000000000) start address2 information register information description dbs bufferram and register of ddp (device bufferram select) 2.8.9 start address1 register f100h (r/w) comp comp dbs dfs ddp_opt gnd ce control logic sram buffer flash core comp comp dbs dfs ddp_opt v dd ce control logic sram buffer flash core ce int chip 1 chip 2 int int in the case of writing register, both registers in chip1 and chip2 will be written regardless of dbs. reading out from register of chip1/ chip2 follows the dbs setting. in using ddp chip, bootram of chip 1 will always be selected regardless of dbs. reading and writing on the dataram of ddp chip is different. only the dataram selected by dbs will be written and read out. this read/write register describes the nand flash block address which will be loaded, programmed, or erased. f100h, default = 0000h note 1) bit 0 should be fixed low at 2x program and 2x cache program. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dfs reserved(0000) fba 1) *comp = comparator
onenand2g(kfg2g16q2m-debx) flash memory 61 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) this read/write register describes the nand flash destination block address which will be copy back programmed. also, this regi s- ter indicates the block address for the first page to be read in cache read operation. f102h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(000000) fcba device number of block fba 2gb 2048 fcba[10:0] start address3 information register information description fcba nand flash copy back block address & block address for the first page to be read in cache read operation 2.8.12 start address4 register f103h (r/w) this read/write register describes the nand flash destination page address in a block and the nand flash destination sector address in a page for copy back programming. also, this register describes the first page and sector address to be loaded in ca che read operation. f103h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(00000000) fcpa fcsa start address4 information item description default value range fcpa nand flash copy back page address & first page address of cache read 000000 000000 ~ 111111, 6 bits for 64 pages fcsa nand flash copy back sector address & first sector address of cache read 00 00 ~ 11, 2 bits for 4 sectors 2.8.11 start address3 register f102h (r/w)
onenand2g(kfg2g16q2m-debx) flash memory 62 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 2.8.14 start address6 register f105h 2.8.15 start address7 register f106h this register is reserved for future use. 2.8.16 start address8 register f107h (r/w) this read/write register describes the nand flash start page address in a block for a page load, copy back program, or program operation and the nand flash start sector address in a page for a load, copy back program, or program operation. f107h, default = 0000h note 1) in case of 2x cache program, the host programs data on same fpa of different planes. 2) in case of synchronous burst block read, cache read operation, 2x program and 2x cache program, fsa has to be set to 00. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved (00000000) fpa 1) fsa 2) start address8 information item description default value range fpa nand flash page address 000000 000000 ~ 111111, 6 bits for 64 pages fsa nand flash sector address 00 00 ~ 11, 2 bits for 4 sectors 2.8.13 start address5 register f104h (r/w) this read/write register describes the number of page in synchronous burst block read. f104h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000) fpc flash page count (fpc) information note) synchronous burst block read are not able to be perforformed with 1 or 2pages. fpc number of page 000000 (default) 64 page 000011 3 page 000100 4 page .. .. 111111 63 page this register is reserved for future use.
onenand2g(kfg2g16q2m-debx) flash memory 63 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) this read/write register describes the bufferram sector count (bsc) and bufferram sector address (bsa). the bufferram sector count (bsc) field specifies the number of sectors to be loaded, programmed, or copy back programmed. at 00 value (the default value), the number of sector is "4". if the internal ram buffer reaches its maximum value of 11, it will count up to 0 value to meet the bsc value. for example, if bsa = 1101, bsc = 00, then the selected bufferram will count up from '1101 o 1110 o 1111 o 1100'. the bufferram sector address (bsa) is the sector 0~3 address in the internal bootram and dataram where data is placed. f200h, default = 0000h note) in case of cache read, bsa has to be set to 1000. and bsc has to be set to 00. in case of synchronous burst block read, bsa has to be set to 1000 or 1100. and bsc has to be set to 00. in case of 2x program or 2x cache program, bsa has to be set to 1000. and bsc has to be set to 00. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000) bsa reserved(000000) bsc start address8 information item description bsa[3] selection bit between bootram and dataram bsa[2] selection bit between dataram0 and dataram1 bsa[1:0] selection bit between sector0 and sector1 in the internal bootram selection bit between sector0 to sector3 in the internal dataram bootram 0 bootram 1 bootram sector: (512 + 16) byte dataram 1_0 dataram 1_1 dataram 1_2 dataram 1_3 dataram1 0000 0001 1100 1101 1110 1111 bsc number of sectors 01 1 sector 10 2 sector 11 3 sector 00 4 sector ^ main area data ^ spare area data bsa dataram 0_0 dataram 0_1 dataram 0_2 dataram 0_3 dataram0 1000 1001 1010 1011 512b 16b 2.8.17 start buffer register f200h (r/w)
onenand2g(kfg2g16q2m-debx) flash memory 64 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) command can be issued by two following methods, and user may select one way or the other to issue appropriate command; 1. write command into command register when int is at ready state. int will automatically turn to busy state as command is issu ed. once the desired operation is completed, int will go back ready state. 2. write 0000h to int bit of interrupt status register, and then write command into command register. once the desired operatio n is completed, int will go back to ready state. (00f0h and 00f3h may be accepted during busy state of some operations. refer to the rightmost column of the command register table below.) f220h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 command note : 1) 0080h programs both main and spare area, while 001ah programs only spare area. refer to chapter 5.9 for nop limits in issuin g these commands. when using 0080h and 001ah command, read-only part in spare area must be masked by ff. (refer to chapter 2.7.2) 2) 2x program is executed by 007d. this command can be used alone and used for ending 2x cache program. 2x cache program is executed by 007f. this command cannot be used alone and must be ended by 007d for the last page progr am of cache pro- gram. (refer to 6.14 and 6.15) 3) reset onenand(=hot reset) command makes the registers and nand flash core into default state. cmd operation acceptable command during busy 0000h load single/multiple sector data unit into buffer 00f0h, 00f3h 0013h load single/multiple spare sector into buffer 00f0h, 00f3h 0080h program single/multiple sector data unit from buffer 1) 00f0h, 00f3h 001ah program single/multiple spare data unit from buffer 00f0h, 00f3h 001bh copy back program operation 00f0h, 00f3h 007dh 2x program operation 2) 00f0h, 00f3h 007fh 2x cache program operation 2) 00f0h, 00f3h 0023h unlock nand array a block 00f0h, 00f3h 002ah lock nand array a block 00f0h, 00f3h 002ch lock-tight nand array a block 00f0h, 00f3h 0027h all block unlock 00f0h, 00f3h 0071h erase verify read 00f0h, 00f3h 000eh cache read 00f0h, 00f3h 000ch finish cache read 00f0h, 00f3h 000ah synchronous burst block read 00f0h, 00f3h 0094h block erase 00f0h, 00f3h 0095h multi-block erase 00f0h, 00f3h 00b0h erase suspend 00f0h, 00f3h 0030h erase resume 00f0h, 00f3h 00f0h reset nand flash core - 00f3h reset onenand 3) - 0065h otp access 00f0h, 00f3h 2.8.18 command register f220h (r/w)
onenand2g(kfg2g16q2m-debx) flash memory 65 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) method 1: manually set int=0 before writing command into command register: manual int mode (1) clear interrupt register (f241h) by writing 0000h into int bit of interrupt register. this operation will make int pin turn low. 1) (2) write command into command register. this will make the device to perform the designated operation. (3) int pin will turn back to high once the operation is completed. 1) write 0 into int bit of interrupt register write command into command register int will automatically turn to high when designated operation is completed. method 2: write command into command register at int ready state: auto int mode (1) write command into command register. this will automatically turn int from high to low. 1) (2) int pin will turn back to high once the operation is completed. 1) to clear interrupt register in command input, user may select one from either following methods. first method is to turn int to low by manually writing 0000h to int bit of interrupt register. 1) second method is input command while int is high, and the device will automatically turn int to low. 1) (second method is equivalent with method used in general nand flash) user may choose the desirable method to clear interrupt register. write command into command register int will automatically turn to busy state int will automatically turn back to ready state when designated operation in completed. note 1) int pin polarity is based on iobe=1 and int pol=1 (default) setting note 1) int pin polarity is based on iobe=1 and int pol=1 (default) setting int pin 1) int bit int pin 1) int bit 2.8.18.1 two methods to clear interrupt register in command input
onenand2g(kfg2g16q2m-debx) flash memory 66 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) this read/write register describes the system configuration. f221h, default =40c0h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r r/w r/w r rm brwl bl ecc rdy pol int pol iobe rdy conf reser ved hf wm bwps read mode (rm) rm read mode 0 asynchronous read(default) 1 synchronous read read mode information[15] item definition description rm read mode selects between asynchronous read mode and synchronous read mode burst read write latency (brwl) information[14:12] item definition description brwl burst read latency / burst write latency specifies the access latency in the burst read / write transfer for the initial access 2.8.19 system configuration 1 register f221h (r, r/w) burst read write latency (brwl) * default value of brwl and hf value is brwl=4, hf=0. for host frequency over 67mhz, brwl should be 6 or 7 while hf is 1. for host frequency range of 40mhz~67mhz, brwl should be set to 4~7 while hf is 0. for host frequency under 40mhz, brwl should be set to 3~7 while hf is 0. brwl latency cycles (read/write) under 40mhz (hf=0) 40mhz~67mhz (hf=0) over 67mhz (hf=1) 000~010 reserved 011 3(up to 40mhz. min) 3(n/a) 3(n/a) 100 (default) 4 4(min.) 4(n/a) 101 5 5 5(n/a) 110 6 6 6(min.) 111 7 7 7
onenand2g(kfg2g16q2m-debx) flash memory 67 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) burst length (bl) note 1) for normal synchronous burst read, setting bl=000 (continuous) will read 1k words depending on the number of clocks. in using synchronous burst block read, setting bl=000 (continuous) will read the amount of data in a block set by number of page r eg- ister. note 2) even in using synchronous burst block read, it is possible to use above burst length by setting bl register by followin g the above table. bl burst length(main) burst length(spare) 000 continuous(default) 001 4 words 010 8 words 011 16 words 100 32 words n/a 101 1k words (block read only) n/a 110~111 reserved burst length (bl) information[11:9] item definition description bl burst length specifies the size of the burst length during a synchronous linear burst read and wrap around. and also burst length during a synchronous linear burst write error correction code (ecc) information[8] item definition description ecc error correction code operation 0 = with correction (default) 1 = without correction (bypassed) rdy polarity (rdypol) information[7] item definition description rdypol rdy signal polarity 1 = high for ready (default) 0 = low for ready int polarity (intpol) information[6] intpol int bit of interrupt status register int pin output 0 0 (busy) high 1 (ready) low 1 (default) 0 (busy) low 1 (ready) high
onenand2g(kfg2g16q2m-debx) flash memory 68 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) i/o buffer enable (iobe) iobe is the i/o buffer enable for the int and rdy signals. at startup, int and rdy outputs are high-z. bits 6 and 7 become vali d after iobe is set to "1". iobe can be reset by a cold reset or by writing "0" to bit 5 of system configuration1 register. i/o buffer enable information[5] item definition description iobe i/o buffer enable for int and rdy signals 0 = disable (default) 1 = enable rdy configuration (rdy conf) rdy configuration information[4] item definition description rdy conf rdy configuration 0=active one clock before valid data(default) 1=active with valid data hf information[2] item definition description hf high frequency selects between hf disable and hf enable hf enable (hf) hf description 0 hf disable (default, 66mhz and under) 1 hf enable (over 66mhz)
onenand2g(kfg2g16q2m-debx) flash memory 69 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) boot buffer write protect status(bwps) boot buffer write protect status information[0] item definition description bwps boot buffer write protect status 0=locked(fixed) write mode (wm) wm write mode 0 asynchronous write(default) 1 synchronous write write mode information[1] item definition description wm write mode selects between asynchronous write mode and synchronouswrite mode mrs(mode register setting) description note) 1. operation not guaranteed for cases not defined in above table. rm wm mode description 0 0 asynch read & asynch write (default) 1 0 sync read & asynch write 1 1 sync read & synch write other case reserved 1)
onenand2g(kfg2g16q2m-debx) flash memory 70 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) this register is reserved for future use. 2.8.21 controller status register f240h (r) this read register shows the overall internal status of the onenand and the controller. f240h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ongo lock load prog erase error sus reserved rstb otp l otp bl plane1 previous plane1 current plane2 previous plane2 current to (0) ongo this bit shows the overall internal status of the onenand device. in 2x cache program operation, ongo bit shows the overall status of 2x cache program process. ongo information[15] item definition description ongo internal device status 0 = ready 1 = busy lock this bit shows whether the host is loading data from the nand flash array into the locked bootram or whether the host is perfor m- ing a program/erase of a locked block of the nand flash array. lock information[14] lock locked/unlocked check result 0 unlocked 1 locked load this bit shows the load operation status. load information[13] item definition description load load operation status 0 = ready (default) 1 = busy or error (see controller status output modes) 2.8.20 system configuration 2 register f222h
onenand2g(kfg2g16q2m-debx) flash memory 71 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) program this bit shows the program operation status. in 2x cache program operation, prog bit shows the overall status of 2x cache program process. program information[12] item definition description prog program operation status 0 = ready (default) 1 = busy or error (see controller status output modes) erase this bit shows the erase operation status. erase information[11] item definition description erase erase operation status 0 = ready (default) 1 = busy or error (see controller status output modes) erase suspend (sus) this bit shows the erase suspend status. sus information[9] sus erase suspend status 0 erase resume(default) 1 erase suspend, program ongoing(susp.), load ongoing(susp.), program fail(susp.), load fail(susp.), invalid command(susp.) error this bit shows the overall error status, including load reset, program reset, and erase reset status. in case of 2x cache program, error bit will show the accumulative error status of 2x cache program operation sg so that if an error occurs during 2x cache program, this bit will stay as fail status, until the end of 2x cache program. in case of 2x program, error bit will indicate the 2x program fail, regardless of plane1 or plane2. error information[10] error sector/page load/program/copyback, program/2x program/ 2x cache program result and invalid command input 0 pass 1 fail
onenand2g(kfg2g16q2m-debx) flash memory 72 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) reset / busy (rstb) this bit shows the reset operation status. rstb information[7] item definition description rstb reset operation status 0 = ready (default) 1 = busy (see controller status output modes) otp lock status (otp l ) this bit shows whether the otp block is locked or unlocked. locking the otp has the effect of a 'write-protect' to guard agains t accidental re-programming of data stored in the otp block. the otp l status bit is automatically updated at power-on. otp lock information[6] otp l otp locked/unlocked status 0 otp block unlock status(default) 1 otp block lock status(disable otp program/erase) 1st block otp lock status (otp bl ) this bit shows whether the 1st block otp is locked or unlocked. locking the 1st block otp has the effect of a 'program/erase protect' to guard against accidental re-programming of data stored in the 1st block. the otp bl status bit is automatically updated at power-on. otp lock information[5] otp bl 1st block otp locked/unlocked status 0 1st block otp unlock status(default) 1 1st block otplock status(disable 1st block otp program/erase) plane1 previous this bit shows the previous program status of plane1 at 2x cache program.this value is invalid only at the first read controll er sta- tus register step of 2x cache program and 2x interleave cache program operation. (refer to 6.15 and 6.16) plane1 previous information[4] plane1 previous status of previous program on plane1 0 pass 1 fail
onenand2g(kfg2g16q2m-debx) flash memory 73 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) time out (to) this bit determines if there is a time out for load, program, copy back program, and erase operations. it is fixed at 'no time out'. to information[0] item definition description to time out 0 = no time out plane1 current this bit shows the current program status of plane1 at final 2x cache program, and 2x program, and 2x interleave cache program. during 2x cache program prior to 2x program command, which will be final 2x cache program, this bit will be invalid (fixed to 0). plane1 current information[3] plane1 current status of current program on plane1 0 pass 1 fail plane2 previous this bit shows the previous program status of plane2 at 2x cache program. this value is invalid only at the first read control ler sta- tus register step of 2x cache program and 2x interleave cache program operation. (refer to 6.15 and 6.16) plane2 previous information[2] plane2 previous status of previous program on plane2 0 pass 1 fail plane2 current this bit shows the current program status of plane2 at final 2x cache program, and 2x program, and 2x interleave cache program. during 2x cache program prior to 2x program command, which will be final 2x cache program, this bit will be invalid (fixed to 0). plane2 current information[1] plane2 current status of current program on plane2 0 pass 1 fail
onenand2g(kfg2g16q2m-debx) flash memory 74 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) controller status register output modes note : 1. erm and/or ers bits in ecc status register at load fail case is 10. (2bits error - uncorrectable) 2. erm and ers bits in ecc status register at load reset case are 00. (no error) 3. multi block erase status should be checked by erase verify read operation. 4. "1" for otp block lock, "0" for otp block unlock. 5. "1" for 1st block otp lock, "0" for 1st block otp unlock. mode controller status register [15:0] [15] [14] [13] [12] [11] [10] [9] [7] [6] [5] [4] [3] [2] [1] [0] ongo lock load prog erase error sus rstb otpl (note4) otpbl (note5) plane1 previous plane1 current plane2 previous plane2 current to load / cache read ongoing 101000000/10/1 0 0 0 0 0 program ongoing 1 0 0 1 0 0 0 0 0/1 0/1 0 0 0 0 0 erase ongoing 100010000/10/1 0 0 0 0 0 reset ongoing 1 0 0 0 0 0 0 1 0/1 0/1 0 0 0 0 0 multi-block erase ongoing 100010000/10/1 0 0 0 0 0 erase verify read ongoing 100000000/10/1 0 0 0 0 0 load / cache read ok 0 0 0 0 0 0 0 0 0/1 0/1 0 0 0 0 0 program ok 000000000/10/1 0 0 0 0 0 erase ok 000000000/10/1 0 0 0 0 0 erase verify read ok 3) 000000000/10/1 0 0 0 0 0 load fail 1) 001001000/10/1 0 0 0 0 0 program fail 000101000/10/1 0 0 0 0 0 erase fail 000011000/10/1 0 0 0 0 0 cache read fail 1 0 1 0 0 1 0 0 0/1 0/1 0 0 0 0 0 erase verify read fail 3) 000011000/10/1 0 0 0 0 0 load reset 2) 001001010/10/1 0 0 0 0 0 program reset 000101010/10/1 0 0 0 0 0 erase reset 000011010/10/1 0 0 0 0 0 erase suspend 0 0 0 0 1 0 1 0 0/1 0/1 0 0 0 0 0 program lock 0 1 0 1 0 1 0 0 0/1 0/1 0 0 0 0 0 erase lock 0 1 0 0 1 1 0 0 0/1 0/1 0 0 0 0 0 load lock(buffer lock) 0 1 1 0 0 1 0 0 0/1 0/1 0 0 0 0 0 otp program fail(lock)0101010011 0 0 0 0 0 otp program fail 0001010000 0 0 0 0 0 otp erase fail 010011000/10/1 0 0 0 0 0 program ongoing(susp.) 1 0 0 1 1 0 1 0 0/1 0/1 0 0 0 0 0 load ongoing(susp.) 1 0 1 0 1 0 1 0 0/1 0/1 0 0 0 0 0 program fail(susp.) 0 0 0 1 1 1 1 0 0/1 0/1 0 0 0 0 0 load fail(susp.) 001011100/10/1 0 0 0 0 0 invalid command 0 0 0 0 0 1 0 0 0/1 0/1 0 0 0 0 0 invalid command(susp.) 0 0 0 0 1 1 1 0 0/1 0/1 0 0 0 0 0
onenand2g(kfg2g16q2m-debx) flash memory 75 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) controller status register output modes (continued) note : 1. erm and/or ers bits in ecc status register at load fail case is 10. (2bits error - uncorrectable) 2. erm and ers bits in ecc status register at load reset case are 00. (no error) 3. "1" for otp block lock, "0" for otp block unlock. 4. "1" for 1st block otp lock, "0" for 1st block otp unlock. 5. this value is invalid in this case. host can recognize the status of the only previous operation. 6. plane previous value is updated immediately after int goes to ready state. after final 2x cache program operation by 2x program command is completed, current and previous program pass/fail status on both plane1 and plane2 will be updated. mode controller status register [15:0] [15] [14] [13] [12] [11] [10] [9] [7] [6] [5] [4] [3] [2] [1] [0] ongo lock load prog erase error sus rstb otpl (note3) otpbl (note4) plane1 previous plane1 current plane2 previous plane2 current to program fail on 2x program (plane1) 000101000/10/1 0 1 0 0 0 program fail on 2x program (plane2) 000101000/10/1 0 0 0 1 0 program fail on 2x program (plane1 & plane2) 000101000/10/1 0 1 0 1 0 previous program fail during 2x cache program (plane1) 100101000/10/1 1(note5)0 0 0 previous program fail during 2x cache program (plane2) 100101000/10/1 0 0 1(note5)0 previous program fail during 2x cache program (plane1 & plane2) 1 0 0 1 0 1 0 0 0/1 0/1 1 (note5) 1 (note5) 0 program fail after final 2x cache program 000101000/10/1 (note6) 0
onenand2g(kfg2g16q2m-debx) flash memory 76 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) this read/write register shows status of the onenand interrupts. in ddp, int register will not be written if dfs is not set. f241h, defaults = 8080h after cold reset; 8010h after warm/hot reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 int reserved(0000000) ri wi ei rsti reserved(0000) 2.8.22 interrupt status register f241h (r/w) interrupt (int) this is the master interrupt bit. the int bit is wired directly to the int pin on the chip. upon writing '0' to the int bit, th e int pin goes low if intpol is high and goes high if intpol is low. int interrupt [15] status conditions default state valid state interrupt function cold warm/hot 11 0 off sets itself to 1 one or more of ri, wi, rsti and ei is set to 1, or 0065h, 0023h, 0071h, 002ah, 0027h and 002ch commands are completed. 0 o 1 pending clears to 0 0 is written to this bit, cold/warm/hot reset is being performed, or command is written to command register in int auto mode 1 o 0 off read interrupt (ri) this is the read interrupt bit. ri interrupt [7] status conditions default state valid state interrupt function cold warm/hot 10 0 off sets itself to 1 at the completion of an load operation (0000h, 000eh, 000ch, 000ah, 0013h, load data into buffer, or boot is done) 0 o 1 pending clears to 0 0 is written to this bit, cold/warm/hot reset is being performed, or command is written to command register in int auto mode 1 o 0 off
onenand2g(kfg2g16q2m-debx) flash memory 77 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) write interrupt (wi) this is the write interrupt bit. wi interrupt [6] status conditions default state valid state interrupt function cold warm/hot 00 0 off sets itself to 1 at the completion of an program operation (0080h, 001ah, 001bh, 007dh, 007fh) 0 o 1 pending clears to 0 0 is written to this bit, cold/warm/hot reset is being performed, or command is written to command register in int auto mode 1 o 0 off erase interrupt (ei) this is the erase interrupt bit. ei interrupt [5] status conditions default state valid state interrupt function cold warm/hot 00 0 off sets itself to 1 at the completion of an erase operation (0094h, 0095h, 0030h) 0 o 1 pending clears to 0 0 is written to this bit, cold/warm/hot reset is being performed, or command is written to command register in int auto mode 1 o 0 off reset interrupt (rsti) this is the reset interrupt bit. rsti interrupt [4] status conditions default state valid state interrupt function cold warm/hot 01 0 off sets itself to 1 at the completion of an reset operation (00b0h, 00f0h, 00f3h or warm reset is released) 0 o 1 pending clears to 0 0 is written to this bit, or command is written to command register in int auto mode 1 o 0 off
onenand2g(kfg2g16q2m-debx) flash memory 78 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 2.8.23 start block address register f24ch (r/w) this register is reserved for future use. 2.8.24 end block address register f24dh 2.8.25 nand flash write protection status register f24eh (r) this read register shows the write protection status of the nand flash memory array. to read the write protection status, fba(dfs and dbs also in case of ddp) has to be set before reading the register . f24eh, default = 0002h write protection status information[2:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000000) us ls lts item definition description us unlocked status 1 = current nand flash block is unlocked ls locked status 1 = current nand flash block is locked or first block of nand flash array is locked to be otp lts locked-tight status 1 = current nand flash block is locked-tight this read/write register shows the nand flash block address in the write protection mode. setting this register precedes a 'loc k block' command, 'unlock block' command, or lock-tight' command. f24ch, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(000000) sba device number of block sba 2gb 2048 [10:0]
onenand2g(kfg2g16q2m-debx) flash memory 79 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 2.8.26 ecc status register ff00h (r) this read register shows the error correction status. the onenand can detect 1- or 2-bit errors and correct 1-bit errors. 3-bit or more error detection and correction is not supported. ecc can be performed on the nand flash main and spare memory areas. the ecc status register can also show the number of errors in a sector as a result of an ecc check in during a load operation. ecc status bits are also updated during a boot loadi ng oper- ation. ecc registers will be reset when another command is issued. ff00h, default = 0000h error status 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 erm3 ers3 erm2 ers2 erm1 ers1 erm0 ers0 erm, ers ecc status 00 no error 01 1 bit error(correctable) 10 2 bit error (uncorrectable) 11 reserved ecc information[15:0] item definition description erm0 1st selected sector of the main bufferram status of errors in the 1st selected sector of the main bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. erm1 2nd selected sector of the main bufferram status of errors in the 2nd selected sector of the main bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. erm2 3rd selected sector of the main bufferram status of errors in the 3rd selected sector of the main bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. erm3 4th selected sector of the main bufferram status of errors in the 4th selected sector of the main bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. ers0 1st selected sector of the spare bufferram status of errors in the 1st selected sector of the spare bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. ers1 2nd selected sector of the spare bufferram status of errors in the 2nd selected sector of the spare bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. ers2 3rd selected sector of the spare bufferram status of errors in the 3rd selected sector of the spare bufferram as a result of an ecc check during a load operation. also updated during a bootload operation. ers3 4th selected sector of the spare bufferram status of errors in the 4th selected sector of the spare bufferram as a result of an ecc check during a load operation. also updated during a bootload operation.
onenand2g(kfg2g16q2m-debx) flash memory 80 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 2.8.28 ecc result of 1 st selected sector, spare area data register ff02h (r) this read register shows the error correction result for the 1st selected sector of the spare area data. ecclogsector0 is the e rror position address for 1.5 words of 2nd and 3rd words in the spare area. e ccposio0 is the error position address which selects 1 of 16 dqs. ecclogsector0 and eccposio0 are also updated at boot loading. ff02h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000) ecclogsector0 eccposio0 this read register shows the error correction result for the 1st selected sector of the main area data. eccposword0 is the erro r position address in the main area data of 256 words. eccposio0 is the error position address which selects 1 of 16 dqs. eccposword0 and eccposio0 are also updated at boot loading. ff01h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000) eccposword0 eccposio0 2.8.27 ecc result of 1 st selected sector, main area data register ff01h (r) this read register shows the error correction result for the 2nd selected sector of the main area data. eccposword1 is the erro r position address in the main area data of 256 words. eccposio1 is the error position address which selects 1 of 16 dqs. eccposword1 and eccposio1 are also updated at boot loading. ff03h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000) eccposword1 eccposio1 2.8.30 ecc result of 2 nd selected sector, spare area data register ff04h (r) this read register shows the error correction result for the 2nd selected sector of the spare area data. ecclogsector1 is the e rror position address for 1.5 words of 2nd and 3rd words in the spare area. eccposio1 is the error position address which selects 1 of 16 dqs. ecclogsector1 and eccposio1 are also updated at boot loading. ff04h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000) ecclogsector1 eccposio1 2.8.29 ecc result of 2 nd selected sector, main area data register ff03h (r)
onenand2g(kfg2g16q2m-debx) flash memory 81 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 2.8.32 ecc result of 3 rd selected sector, spare area data register ff06h (r) this read register shows the error correction result for the 3rd selected sector of the spare area data. ecclogsector2 is the e rror position address for 1.5 words of 2nd and 3rd words in the spare area. e ccposio2 is the error position address which selects 1 of 16 dqs. ecclogsector2 and eccposio2 are also updated at boot loading. ff06h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000) ecclogsector2 eccposio2 2.8.31 ecc result of 3 rd selected sector, main area data register ff05h (r) this read register shows the error correction result for the 3rd selected sector of the main area data. eccposword2 is the erro r position address in the main area data of 256 words. eccposio2 is the error position address which selects 1 of 16 dqs. eccposword2 and eccposio2 are also updated at boot loading. ff05h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000) eccposword2 eccposio2 this read register shows the error correction result for the 4th selected sector of the main area data. eccposword3 is the erro r position address in the main area data of 256 words. eccposio3 is the error position address which selects 1 of 16 dqs. eccposword3 and eccposio3 are also updated at boot loading. ff07h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000) eccposword3 eccposio3 2.8.34 ecc result of 4 th selected sector, spare area data register ff08h (r) this read register shows the error correction result for the 4th selected sector of the spare area data. ecclogsector3 is the e rror position address for 1.5 words of 2nd and 3rd words in the spare area. eccposio3 is the error position address which selects 1 of 16 dqs. ecclogsector3 and eccposio3 are also updated at boot loading. ff08h, default = 0000h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved(0000000000) ecclogsector3 eccposio3 2.8.33 ecc result of 4 th selected sector, main area data register ff07h (r)
onenand2g(kfg2g16q2m-debx) flash memory 82 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) ecc log sector ecclogsector0~ecclogsector3 indicates the error position in the 2nd word and lsb of 3rd word in the spare area. refer to note 2 in chapter 2.7.2 ecclogsector information [5:4] ecclogsector error position 00 2nd word 01 3rd word 10, 11 reserved
onenand2g(kfg2g16q2m-debx) flash memory 83 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) this section of the datasheet discusses the operation of the onenand device. it is followed by ac/dc characteristics and timing diagrams which may be consulted for further information. the onenand supports a limited command-based interface in addition to a register-based interface for performing operations on t he device. 3.1 command based operation the command-based interface is active in the boot partition. commands can only be written with a boot area address. boot area d ata is only returned if no command has been issued prior to the read. the entire address range, except for the boot area, can be used for the data buffer. all commands are written to the boot parti tion. writes outside the boot partition are treated as normal writes to the buffers or registers. the command consists of one or more cycles depending on the command. after completion of the command the device starts its exe- cution. writing incorrect information including address and data to the boot partition or writing an improper command will term inate the previous command sequence and make the device enter the ready status. the defined valid command sequences are stated in command sequences table. command based operations are mainly used when onenand is used as booting device, and all command based operations only supports asynchronous reads and writes. with ddp, command based operation except reset is applicable only on chip1. command sequences note: 1) bp(boot partition) : bootram area [0000h ~ 01ffh, 8000h ~ 800fh]. 2) load data into buffer operation is available within a block(128kb) (chip1 only in case of ddp) 3) load 2kb unit into dataram0. current start address(fpa) is automatically incremented by 2kb unit after the load. 4) 0000h -> data is manufacturer id (chip1 only in case of ddp) 0001h -> data is device id (chip1 only in case of ddp) 0002h -> current block write protection status (chip1 only in case of ddp) 5) we toggling can terminate read identification data operation. command definition cycles 1st cycle 2nd cycle reset onenand add 1 bp 1) data 00f0h load data into buffer 2) add 2 bp bp data 00e0h 0000h 3) read identification data 5) add 2 bp xxxxh 4) data 0090h data 3.0 device operation
onenand2g(kfg2g16q2m-debx) flash memory 84 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the buffer memory can be read by addressing a read to the desired buffer area. 3.1.2 writing data to buffer the buffer memory can be written to by addressing a write to a desired buffer area. 3.1.3 reset onenand command the reset command is given by writing 00f0h to the boot partition address. reset will return all default values into the device . 3.1.4 load data into buffer command load data into buffer command is a two-cycle command. two sequential designated command activates this operation. sequentially writing 00e0h and 0000h to the boot partition [0000h~01ffh, 8000h~800fh] will load one page to dataram0. this operation refers to fba and fpa. fsa, bsa, and bsc are not considered. at the end of this operation, fpa will be automatically increased by 1. so continuous issue of this command will sequentially l oad data in next page to dataram0. this page address increment is restricted within a block. the default value of fba and fpa is 0. therefore, initial issue of this command after power on will load the first page of memo ry, which is usually boot code. 3.1.5 read identification data command the read identification data command consists of two cycles. it gives out the devices identification data according to the give n address. the first cycle is 0090h to the boot partition address and second cycle is read from the addresses specified in identi fication data description table. 3.1.1 reading data from buffer identification data description note 1) refer to device id register (chapter 2.8.3) 2)to read the write protection status, fba has to be set before issuing this command. address data out 0000h manufacturer id (00ech) 0001h device id 1) 0002h current block write protection status 2)
onenand2g(kfg2g16q2m-debx) flash memory 85 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 3.2 device bus operation the device bus operations are shown in the table below. note : l=v il (low), h=v ih (high), x=dont care. operation ce oe we add0~15 dq0~15 rp clk avd standby h x x x high-z h x x warm reset xxxxhigh-zlxx asynchronous write l h l add. in data in h l x asynchronous read l l h add. in data out h l or l load initial burst read l h h add. in x h burst read l l h x burst data out h terminate burst read cycle hxhxhigh-zhxx terminate burst read cycle via rp xxxxhigh-zlxx terminate current burst read cycle and start new burst read cycle h h add in high-z h load initial burst write l h l add. in x h burst write l h x x burst data in hx terminate burst write cycle hxxxhigh-zhxx terminate burst write cycle via rp xxxxhigh-zlxx terminate current burst write cycle and start new burst write cycle h l add in high-z h x
onenand2g(kfg2g16q2m-debx) flash memory 86 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the one nand has 4 reset modes: cold/warm/hot reset, and nand flash array reset. section 3.3 discusses the operation of these reset modes. the register reset table shows the which registers are affected by the various types or reset operations. internal register reset table note: 1) rdypol, intpol, iobe are reset by cold reset. the other bits except otp l and otp bl are reset by cold/warm/hot reset. 2) ecc status register & ecc result registers are reset when any command is issued. 3) refer to device id register f001h. internal registers default cold reset warm reset (rp ) hot reset (00f3h) hot reset (bp-f0h) nand flash core reset (00f0h) f000h manufacturer id register (r) 00ech n/a n/a n/a n/a f001h device id register (r): onenand (note 3) n/a n/a n/a n/a f002h version id register (r) n/a n/a n/a n/a n/a f003h data buffer size register (r) 0800h n/a n/a n/a n/a f004h boot buffer size register (r) 0200h n/a n/a n/a n/a f005h amount of buffers register (r) 0201h n/a n/a n/a n/a f006h technology register (r) 0000h n/a n/a n/a n/a f100h start address1 register (r/w): dfs, fba 0000h 0000h 0000h 0000h n/a f101h start address2 register (r/w): dbs 0000h 0000h 0000h 0000h n/a f102h start address3 register (r/w): fcba 0000h 0000h 0000h 0000h n/a f103h start address4 register (r/w): fcpa, fcsa 0000h 0000h 0000h 0000h n/a f104h start address5 register (r/w): fpc 0000h 0000h 0000h 0000h n/a f107h start address8 register (r/w): fpa, fsa 0000h 0000h 0000h 0000h n/a f200h start buffer register (r/w): bsa, bsc 0000h 0000h 0000h 0000h n/a f220h command register (r/w) 0000h 0000h 0000h 0000h n/a f221h system configuration 1 register (r/w) 40c0h 40c0h (note1) (note1) n/a f240h controller status register (r) 0000h 0000h 0000h 0000h n/a f241h interrupt status register (r/w) - 8080h 8010h 8010h n/a f24ch start block address (r/w) : sba 0000h 0000h 0000h 0000h n/a f24dh end block address: n/a n/a n/a n/a n/a n/a f24eh nand flash write protection status (r) 0002h 0002h 0002h n/a n/a ff00h ecc status register (r) (note2) 0000h 0000h 0000h 0000h n/a ff01h ecc result of sector 0 main area data register(r) 0000h 0000h 0000h 0000h n/a ff02h ecc result of sector 0 spare area data register (r) 0000h 0000h 0000h 0000h n/a ff03h ecc result of sector 1 main area data register(r) 0000h 0000h 0000h 0000h n/a ff04h ecc result of sector 1 spare area data register (r) 0000h 0000h 0000h 0000h n/a ff05h ecc result of sector 2 main area data register(r) 0000h 0000h 0000h 0000h n/a ff06h ecc result of sector 2 spare area data register (r) 0000h 0000h 0000h 0000h n/a ff07h ecc result of sector 3 main area data register(r) 0000h 0000h 0000h 0000h n/a ff08h ecc result of sector 3 spare area data register (r) 0000h 0000h 0000h 0000h n/a 3.3 reset mode operation
onenand2g(kfg2g16q2m-debx) flash memory 87 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 3.3.2 warm reset mode operation see timing diagrams 6.19 a warm reset means that the host resets the device by using the rp pin. when the a rp low is issued, the device logic stops all cur- rent operations and executes internal reset operation and resets current nand flash core operation synchronized with the falling edge of rp . during an internal reset operation, the device initializes internal registers and makes output signals go to default status. the bufferram data is kept unchanged after warm/hot reset operations. the device guarantees the logic reset operation in case rp pulse is longer than trp min(200ns). the device may reset if trp < trp min(200ns), but this is not guaranteed. warm reset will abort the current nand flash core operation. during a warm reset, the content of memory cells being altered is no longer valid as the data will be partially programmed or erased. warm reset has no effect on contents of bootram and dataram. 3.3.3 hot reset mode operation see timing diagram 6.20 a hot reset means that the host resets the device by reset command. the reset command can be either command based or register based. upon receiving the reset command, the device logic stops all current operation and executes an internal reset operation and resets the current nand flash core operation. during an internal reset operation, the device initializes internal registers and makes output signals go to default status. th e bufferram data is kept unchanged after warm/hot reset operations. hot reset has no effect on contents of bootram and dataram. 3.3.4 nand flash core reset mode operation see timing diagram 6.21 the host can reset the nand flash core operation by issuing a nand flash core reset command. nand flash core reset will abort the current nand flash core operation. during a nand flash core reset, the content of memory cells being altered is no lo nger valid as the data will be partially programmed or erased. nand flash core reset has an effect on neither contents of bootram and dataram nor register values. at system power-up, the voltage detector in the device detects the rising edge of vcc and releases an internal power-up reset s ignal. this triggers bootcode loading. bootcode loading means that the boot loader in the device copies designated sized data (1kb) fr om the beginning of memory into the bootram. this sequence is the cold reset of onenand. boot code copy operation activates after 400us from the moment that vcc reaches 1.7v. the system power must be kept at operating voltage (refer to 4.2) once it reaches 1.7v. it takes approximately 70us to copy 1kb of bootcode. upon completion of loading into the bootram, it is available to be read by the host. the int pin is not available until after iobe = 1 and iobe bit can be changed by host. 3.3.1 cold reset mode operation see timing diagram 6.18
onenand2g(kfg2g16q2m-debx) flash memory 88 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the onenand can be write-protected to prevent re-programming or erasure of data. the areas of write-protection are the bootram, and the nand flash array. 3.4.1 bootram write protection operation at system power-up, voltage detector in the device detects the rising edge of vcc and releases the internal power-up reset sign al which triggers bootcode loading. and the designated size data(1kb) is copied from the first page of the first block in the nand flash array to the bootram. after the bootcode loading is completed, the bootram is always locked to protect the boot code from the accidental write. 3.4.2 nand flash array write protection operation the device has both hardware and software write protection of the nand flash array. hardware write protection operation the hardware write protection operation is implemented by executing a cold or warm reset. on power up, the nand flash array is in its default, locked state. the entire nand flash array goes to a locked state after a cold or warm reset. software write protection operation the software write protection operation is implemented by writing a lock command (002ah) or a lock-tight command (002ch) to command register (f220h). lock (002ah) and lock-tight (002ch) commands write protects the block defined in the start block address register f24ch. 3.4.3 nand array write protection states there are three lock states in the nand array: unlocked, locked, and locked-tight. onenand2g supports lock/unlock/lock-tight by one block, and all block unlock at once. note that lock-tighten block will remain lock-tight even though all block unlock command is issued. write protection status the current block write protection status can be read in nand flash write protection status register(f24eh). there are three bi ts - us, ls, lts -, which are not cleared by hot reset. these write protection status registers are updated when fba is set, and whe n write protection command is entered. the followings summarize locking status. example) in default, [2:0] values are 010. -> if host executes unlock block operation, then [2:0] values turn to 100. -> if host executes lock-tight block operation, then [2:0] values turn to 001. 3.4 write protection operation
onenand2g(kfg2g16q2m-debx) flash memory 89 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) an unlocked block can be programmed or erased. the status of an unlocked block can be changed to locked or locked-tight using the appropriate software command. (locked-tight state can be achieved via lock-tight command which follows lock command) only one block can be released from lock state to unlock state with unlock command and addresses. the unlocked block can be changed with new lock command. therefore, each block has its own lock/unlock/lock-tight state. also, by issuing all block unlock command, all blocks excluding lock-tighten blocks will turn to unlocked state. unlock command sequence: start block address+unlock block command (0023h) unlocked 3.4.3.2 locked nand array write protection state a locked block cannot be programmed or erased. all blocks default to a locked state following a cold or warm reset. unlocked blocks can be changed to locked using the lock block command. the status of a locked block can be changed to unlocked or locked-tight using the appropriate software command. lock command sequence: start block address+lock block command (002ah) locked 3.4.3.1 unlocked nand array write protection state all block unlock command sequence: start block address(000h)+all block unlock command (0027h) note) even though sba is fixed to 000h, unlock will be done for all block. unlocked
onenand2g(kfg2g16q2m-debx) flash memory 90 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) a block that is in a locked-tight state can only be changed to locked state after a cold or warm reset. unlock and lock command sequences will not affect its state. this is an added level of write protection security. a block must first be set to a locked state before it can be changed to locked-tight using the lock-tight command. locked-tight blocks will revert to a locked state following a cold or warm reset. lock-tight command sequence: start block address+lock-tight block command (002ch) locked-tight 3.4.3.3 locked-tight nand array write protection state 3.4.4 nand flash array write protection state diagram power on start block address +unlock block command rp pin: high & lock block command rp pin: high & +lock-tight block command rp pin: high & cold reset or unlock lock lock-tight lock lock warm reset start block address lock lock start block address cold reset or warm reset or unlock start block address (000h) rp pin: high & +all block unlock command *note: if the 1st block is set to be otp, block 0 will always be lock status
onenand2g(kfg2g16q2m-debx) flash memory 91 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) data protection operation flow diagram note 1) write 0 to interrupt register step may be ignored when using int auto mode. refer to chapter 2.8.18.1 start lock/unlock/lock-tight write lock/unlock/lock-tight add: f220h dq=002ah/0023h/002ch wait for int register low to high transition add: f241h dq[15]=int write 0 to interrupt register 1) add: f241h dq=0000h command completed * dfs, dbs is for ddp * samsung strongly recommends to follow the above flow chart write dfs*, of flash add: f100h dq=dfs* write sba of flash add: f24ch dq=sba select dataram for ddp add: f101h dq=dbs
onenand2g(kfg2g16q2m-debx) flash memory 92 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) all block unlock flow diagram start unlock all block write all block unlock add: f220h dq=0027h wait for int register low to high transition add: f241h dq[15]=int command completed note 1) write 0 to interrupt register step may be ignored when using int auto mode. refer to chapter 2.8.18.1 * samsung strongly recommends to follow the above flow chart * dfs, dbs is for ddp write 0 to interrupt register 1) add: f241h dq=0000h write dfs*, of flash add: f100h dq=dfs* write sba of flash add: f24ch dq=sba(000h) select dataram for ddp add: f101h dq=dbs
onenand2g(kfg2g16q2m-debx) flash memory 93 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the device is designed to offer protection from any involuntary program/erase during power-transitions. rp pin which provides hardware protection must be kept at vil before vcc drops to 1.5v. 3.6 load operation see timing diagrams 6.12 the load operation is initiated by setting up the start address from which the data is to be loaded. the load command is issued in order to initiate the load. during a load operation, the device: -transfers the data from nand flash array into the bufferram -ecc is checked and any detected and corrected error is reported in the status response as well as any unrecoverable error. once the bufferram has been filled, an interrupt is issued to the host so that the contents of the bufferram can be read. the r ead from the bufferram can be an asynchronous read mode or synchronous read mode. the status information related to load operation can be checked by the host if required. the device has a dual data buffer memory architecture (dataram0, dataram1), each 2kb in size. each dataram buffer has 4 sectors. the device is capable of independent and simultaneous data-read operation from one data buffer and data-load operation to the other data buffer. refer to the information for more details in section 3.12.1, "read-while-load operation". load operation flow chart diagram 3.5 data protection during power down operation see timing diagram 6.22 start write dfs*, fba of flash add: f100h dq=dfs, fba write fpa, fsa of flash add: f107h dq=fpa, fsa write bsa, bsc of dataram add: f200h dq=bsa, bsc select dataram for ddp add: f101h dq=dbs write load command add: f220h dq=0000h or 0013h wait for int register low to high transition add: f241h dq[15]=int read controller add: f240h dq[10]=error dq[10]=0? no yes * dbs, dfs is for ddp status register host reads data from dataram read completed map out write 0 to interrupt register 1) add: f241h dq=0000h note 1) write 0 to interrupt register step may be ignored when using int auto mode. refer to chapter 2.8.18.1
onenand2g(kfg2g16q2m-debx) flash memory 94 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the device has two read modes; asynchronous read and synchronous burst read. the initial state machine automatically sets the device into the asynchronous read mode (rm=0) to prevent the spurious altering of memory content upon device power up or after a hardware reset. no commands are required to retrieve data in asynchronous read mode. the synchronous read mode is enabled by setting rm bit of system configuration1 register (f221h) to synchronous read mode (rm=1). see section 2.8.19 for more information about system configuration1 register. in an asynchronous read mode, data is output with respect to a logic input, avd . output data will appear on dq15-dq0 when a valid address is asserted on a15-a0 while driving avd and ce to vil. we is held at vih. the function of the avd signal is to latch the valid address. address access time from avd low (taa) is equal to the delay from valid addresses to valid output data. the chip enable access time (tce) is equal to the delay from the falling edge of ce to valid data at the outputs. the output enable access time (toe) is the delay from the falling edge of oe to valid data at the output. 3.7.2 synchronous read mode operation (rm=1, wm=x) see timing diagrams 6.1 and 6.2 in a synchronous read mode, data is output with respect to a clock input. the device is capable of a continuous linear burst operation and a fixed-length linear burst operation of a preset length. bur st address sequences for continuous and fixed-length burst operations are shown in the table below. burst address sequences in the burst mode, the initial word will be output asynchronously, regardless of brwl. while the following words will be determ ined by brwl value. the latency is determined by the host based on the brwl bit setting in the system configuration 1 register. the default brwl is 4 latency cycles. at clock frequencies of 40mhz or lower, latency cycles can be reduced to 3. brwl can be set up to 7 latency cyc les. the brwl registers can be read during a burst read mode by using the avd signal with an address. start addr. burst address sequence(decimal) continuous burst 4-word burst 8-word burst 16-word burst 32-word burst wrap around 0 0-1-2-3-4-5-6-..-0-1... 0-1-2-3-0... 0-1-2-3-4-5-6-7-0... 0-1-2-3-4-....-13-14-15-0... 0-1-2-3-4-....-29-30-31-0... 1 1-2-3-4-5-6-7-..-1-2... 1-2-3-0-1... 1-2-3-4-5-6-7-0-1... 1-2-3-4-5-....-14-15-0-1... 1-2-3-4-5-....-30-31-0-1... 2 2-3-4-5-6-7-8-..-2-3... 2-3-0-1-2... 2-3-4-5-6-7-0-1-2... 2-3-4-5-6-....-15-0-1-2... 2-3-4-5-6-....-31-0-1-2... . . . . . . . . . . . . 3.7.1 asynchronous read mode operation (rm=0, wm=x) see timing diagrams 6.5, 6.6, 6.7 and 6.8 3.7 read operation see timing diagrams 6.1, 6.2, 6.5, 6.6, 6.7 and 6.8
onenand2g(kfg2g16q2m-debx) flash memory 95 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) first clock cycle the initial word is output at tiaa after the rising edge of the first clk cycle. the rdy output indicates the initial word is r eady to the system by pulsing high. if the device is accessed synchronously while it is set to asynchronous read mode, the first data can s till be read out. subsequent clock cycles subsequent words are output (burst access time from valid clock to output) tba after the rising edge of each successive clock cycle, which automatically increments the internal address counter. terminating burst read the device will continue to output sequential burst data until the system asserts ce high, or rp low, wrapping around until it reaches the designated address (see section 2.7.3 for address map information). alternately, a cold/warm/hot reset, or a we low pulse will terminate the burst read operation. synchronous read boundary division add.map(word order) bootram main(0.5kw) 0000h~01ffh bufferram0 main(1kw) 0200h~05ffh bufferram1 main(1kw) 0600h~09ffh reserved main 0a00h~7fffh bootram spare(16w) 8000h~800fh bufferram0 spare(32w) 8010h~802fh bufferram1 spare(32w) 8030h~804fh reserved spare 8050h~8fffh reserved register 9000h~efffh register(4kw) f000h~ffffh not support not support * reserved area is not availa ble on synchronous read 3.7.2.2 4-, 8-, 16-, 32-word linear burst read operation see timing diagram 6.1 an alternate burst read mode enables a fixed number of words to be read from consecutive address. the device supports a burst read from consecutive addresses of 4-, 8-, 16-, and 32-words with a linear-wrap around. when the la st word in the burst has been reached, assert ce and oe high to terminate the operation. in this mode, the start address for the burst read can be any address of the address map with one exception. the device does no t support a 32-word linear burst read on the spare area of the bufferram. not support not support not support 3.7.2.1 continuous linear burst read operation see timing diagram 6.2
onenand2g(kfg2g16q2m-debx) flash memory 96 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) upon power up, the number of initial clock cycles from valid address (avd ) to initial data defaults to four clocks. the number of clock cycles (n) which are inserted after the clock which is latching the address. the host can read the first da ta with the (n+1)th rising edge. the number of total initial access cycles is programmable from three to seven cycles. after the number of programmed burst cloc k cycles is reached, the rising edge of the next clock cycle triggers the next burst data. four clock burst read latency (brwl=4 case) 3.7.3 handshaking operation the handshaking feature allows the host system to simply monitor the rdy signal from the device to determine when the initial word of burst data is ready to be read. to set the number of initial cycles for optimal burst mode, the host should use the programmable burst read latency configurati on (see section 2.8.19, "system configuration1 register"). the rising edge of rdy which is derived at one cycle prior of data fetch clock indicates the initial word of valid burst data. 3.7.2.3 programmable burst read latency operation see timing diagrams 6.1 and 6.2 when the ce or oe input is at v ih , output from the device is disabled. the outputs are placed in the high impedance state. 3.7.4 output disable mode operation *note: brwl=4, hf=0 is recommended for 40mhz~66mhz. for frequency over 66mhz, brwl should be 6 or 7 while hf=1. also, for frequency under 40mhz, brwl can be reduced to 3, and hf=0. t iaa hi-z ce clk avd oe rdy | | t rdys t rdya dq0: dq15 d6 d7 d0 d1 d2 d3 d7 d0 hi-z | | | | 0123 -1 t ba rising edge of the clock cycle following last read latency triggers next burst data a0: a15 valid address 4
onenand2g(kfg2g16q2m-debx) flash memory 97 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) a normal load operation(0000h) consists of sequential operation of sensing from nand flash array to page buffer and transfer - ring from page buffer to dataram. cache read is a method of improving the data read throughput performance of the device by allowing new data to be transferred from the nand flash array memory into a page buffer while the previous data that was requested is transferred from the page buffer to the dataram. this method is called transfer-while sensing operation. this ability to simultaneously sense a new page shortens the read cycle resulting in performance increase to 108mbytes/second. cache read mode is designed to continuously read massive data from random address at a high speed. the characteristics of cache read is as follows; -before entering first cache read command(000eh), address of two pages which will be read will be set on address registers. t he register information follows on next line. -register used for first page is copy-back registers (fcba, fcpa and fcsa). and the registers used for addressing second page and following cache read are normal address registers(fba, fpa and fsa). at cache read operation, fcsa and fsa must be set to "00". -bsa setting is only required once at first cache read cycle. from the following cycles, bsa will be automatically switched t o select dataram0 and dataram1 alternately. -bsc must be fixed as "00" -to eliminate performance degradation during ready state(int high state) due to register setting time, setting registers (fba, fpa and fsa) during busy state(int low state) is possible from third address setting onwards. -inputting other commands, which is not related to cache read, between first cache read command and finish cache read command will fail the cache read operation. -in case of performing cache read at int auto mode, int low setting is not necessary. int will automatically go to low when cac he read command is issued. -if host changes dbs or dfs to access the other chip for ddp while performing cache read operation, it will fail the cache read oper- ation. a cache-read flow chart is on the following page. dataram page buffer selected page nand flash array 1) sensing 1) transfer 2) read host transfer-while sensing operation 3.8 cache read operation (rm=x, wm=x)
onenand2g(kfg2g16q2m-debx) flash memory 98 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) cache read flow chart start write fcba of flash add: f102h dq=fcba write fcpa, fcsa 2) of flash add: f103h dq=fcpa, fcsa write bsa 1) , bsc 2) of flash add: f200h dq=bsa, bsc wait for int high state add: f241h dq[15]=int write fpa, fsa 2) of flash add: f107h dq=fpa, fsa write first cache read command add: f220h dq=000eh map out dq[10]=0? read controller status add: f240h dq[10]=error no yes register (n-1)th cache read? no yes write 0 to interrupt register 5) add: f241h dq=0000h write fpa, fsa 2) of flash 4) add: f107h dq=fpa, fsa write 0 to interrupt register 5) add: f241h dq=0000h write cache read command add: f220h dq=000eh host reads data from dataram 6) write fpa, fsa 2) of flash add: f107h dq=fpa, fsa wait for int high state add: f241h dq[15]=int read controller status add: f240h dq[10]=error register dq[10]=0? no yes write 0 to interrupt register 5) add: f241h dq=0000h write cache read command @(n-1)th read host reads data from dataram wait for int high state add: f241h dq[15]=int read controller status add: f240h dq[10]=error register dq[10]=0? yes no add: f220h dq=000eh end add: f220h dq=000ch host reads data from dataram wait for int high state add: f241h dq[15]=int read controller status add: f240h dq[10]=error register dq[10]=0? yes no host reads data from dataram write finish cache read command @nth read write 0 to interrupt register 5) add: f241h dq=0000h write dfs*, fba of flash add: f100h dq=dfs, fba * dbs, dfs is for ddp write dfs*, fba of flash 4) add: f100h dq=dfs, fba write dfs*, fba of flash add: f100h dq=dfs, fba read controller status dq[15]=ongo & dq[13]=load register add: f240h dq[15]=1 & dq[13]=1 ? yes no select dataram for ddp 3) 4) add: f101h dq=dbs note; 1) in case of first cycle cache read, bsa must be set to 1000 or 1100, and from second cycle cache read, bsa will automatically be switched between dataram0 and dataram1. 2) bsc, fsa and fcsa must be set to "00". 3) if host changes dbs or dfs while performing cache read operation, it will fail the cache read operation. 4) these steps can also be set during int=high, before next cache read command 5) write 0 to interrupt register step may be ignored when using int auto mode. refer to chapter 2.8.18.1 6) when host reads data from dataram, host should start from the dataram of the first set bsa, and then next dataram alternately, as the number of cache read.
onenand2g(kfg2g16q2m-debx) flash memory 99 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) int add/ 1st address host reads 1st data from dataram | setting 2nd address setting command setting 4th address setting command setting status read status read | host reads (n-2)th data from dataram | command setting status read host reads (n-1)th data from dataram | command setting status read finish host reads nth data from dataram -1st address setting : address setting operation for first page load(fcba, fcpa, fcsa, and bsa). -2nd~nth address setting : address setting operation from 2nd~nth page load(fba and fpa). -command setting : it consists of writing 0 to interrupt register and writing command to command register. (in int auto mode, writing 0 to interrupt register may be ignored) -status read : it consists of int high state checking and controller status register checking step. -host read 1st~nth data from dataram : during this step, host can read data from dataram by any read mode which supported by on enand. -finish command setting : if host want to finish cache read, host can finish cahce read by issuing finish command. -controller status register status: during cache read - ongoing / load ecc error during cache read - ongoing / load / error ecc error at finish cache read - load / error note 1) 3rd~nth address can be set during int=low, and also during int=high, before next cache read command. cache read diagram dq int add/ 0~15 dq 0~15 (cont.) (cont.) 3rd address setting 1)
onenand2g(kfg2g16q2m-debx) flash memory 100 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) onenand is internally composed of two datarams and nand flash array. and for host to read data from nand cell array, load operation which moves data from nand cell array to dataram is required. after this load operation, host may use various read mode, such as synchronous burst read or asynchronous read, to read data from onenand. but these types of read mode require issuing of address and load command for each page, and cpu had the burden of calculating address to be read. to solve this burden, synchronous burst block read mode is introduced, which enables host to read the data of succeeding page with clk toggle, after initial address setting and command input. this synchronous burst block read is intended to transfer continuous massive data in nand flash array at high speed, and it sequentially reads out data only from main area, whe re large sized data is stored. the addresses set for synchronous burst block read is start page address(fpa), number of page(fpc) and bsa. note that the number of page set by fpc should not exceed the block boundary, since page wrap-around is not supported. and from the start pag e address to desired number of page, synchronous burst block read will output data by clk toggle and ce enable/disable. fpc must be set from 3pages to 64pages. (refer to 2.8.13) the host can access onenand during synchronous burst block read in between every 1-page of read cycle. when host accesses datarams, the address of datarams must be a multiple of 4 in order to prevent from data corruption. in doing this, int pin or bit is used as indicator signal. thus, before host reads 1-page data from dataram, host must confirm int pin or bit return low to hig h, and then enable ce to read 1-page of data. and when host read operation for this 1-page is done, int will automatically turn low. note that int auto mode is a mandatory option for synchronous burst block read, and we must always be set high throughout this ope- artion. therefore, the steps are as follows; 1. host will deassert ce of onenand after checking the indicator(int pin / bit) turn low. 2. and then assert the ce of other device to perform another operation. 3. then disable this other device by deasserting ce when desired operation is done. 4. once the host confirms the int pin or bit of onenand turn low to high, host may read the data of following page by asserting ce (refer to synchronous burst block read operation timing). note that return of int pin to high implies the internal load operation from nand flash array to dataram is complete. also, eve n when the host is not accessing other device, this assert/deassert of ce step is neccessary. note that return of int pin to high implies the internal load operation from nand flash array to dataram is complete. also, whe n the host is not accessing other device, this assert/deassert of ce step is neccessary. to read data from this loaded 1 page, same 4, 8, 16, 32, continuous (1k word) linear burst read operation of synchronous burst read may be utilized. in conclusion, by supporting indicator signal such as int pin or bit, host may access other device without terminating continuo us lin- ear synchronous burst block read, while using continuous linear burst read mode as synchronous block read within 1 block betwee n every (n) page and (n+1) page. (refer to synchronous burst block read boundary) 3.9 synchronous burst block read operation (rm=1,wm=x) see timing diagram 6.3 and 6.4
onenand2g(kfg2g16q2m-debx) flash memory 101 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) first clock cycle the initial word is output at tiaa after the rising edge of the first clk cycle. the rdy output indicates the initial word is r eady to the system by pulsing high. if the device is accessed synchronously while it is set to asynchronous read mode, the first data can s till be read out. subsequent clock cycles subsequent words are output (burst access time from valid clock to output) tba after the rising edge of each successive clock cycle, which automatically increments the internal address counter. terminating synchronous burst block read the device will continue to output sequential burst data until the system resets (cold/warm/hot reset), wrapping around until i t reaches the designated address (see section 3.9.1 for burst address sequence). asserting we low is prohibited during synchronous burst block read operation. in a synchronous burst block read, data is output with respect to a clock input. onenand is capable of a continuous linear burst operation within one block size and a fixed-length linear burst operation of a preset length. note that only int pin is valid indicator signal for continuous linear burst read operation but both int pin and bit are valid for a fixed- length linear burst operation. burst address sequence for continuous and fixed-length burst operations are shown in the table below. burst address sequences same as the normal burst mode, the initial word will be output asynchronously, regardless of brwl while the following words wil l be determined by brwl value. the latency is determined by the host based on the brwl bit setting in the system configuration 1 register. the default brwl is 4 latency cycles. at clock frequencies of 40mhz or lower, latency cycles can be reduced to 3, at frequency range from 40mhz to 67mhz, latency cycle should be over 4. and at 83mhz frequency, brwl should be set to 6. brwl can be set up to 7 latency cycles. the brwl registers can be read during a burst read mode by using the avd signal with an address. start addr. burst address sequence(decimal) continuous burst 4-word burst 8-word burst 16-word burst 32-word burst 1k-word burst 0 0-1-2-3-4-5-6... 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-....-13-14-15 0-1-2-3-4-....-29- 30-31 0-1-2-3-4-....-1022-1023 1 1-2-3-4-5-6-7... 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-....-14-15-0 1-2-3-4-5-....-30- 31-0 1-2-3-4-5-....-1022-1023-0 2 2-3-4-5-6-7-8... 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-....-15-0-1 2-3-4-5-6-....-31 -0-1 2-3-4-5-6-....-1023-0-1 . . . . . . . . . . . . . . 3.9.2 continuous linear burst read operation during synchronous burst block read mode 3.9.1 burst address sequence during synchronous burst block read mode
onenand2g(kfg2g16q2m-debx) flash memory 102 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) synchronous burst block read boundary read sequence for single plane device :note that only main area data is read. main area ^ spare area page 0 page 63 . . . not supported
onenand2g(kfg2g16q2m-debx) flash memory 103 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) same as normal linear burst read, synchronous burst block read enables a fixed number of words to be read from consecutive address. the device supports a burst read from consecutive addresses of 4-, 8-, 16-, 32- and 1k-words with no wrap. (note that wrap-around is not supported in synchronous burst block read) 3.9.4 programmable burst read latency operation during synchro- nous burst block read mode synchronous burst block read mode have progrmmable burst read latency just same manner as normal synchronous burst read mode. upon power up, the number of initial clock cycles from valid address (avd ) to initial data defaults to four clocks. the number of clock cycles (n) which are inserted after the clock which is latching the address. the host can read the first da ta with the (n+1)th rising edge. the number of total initial access cycles is programmable from three to seven cycles. after the number of programmed burst cloc k cycles is reached, the rising edge of the next clock cycle triggers the next burst data. four clock burst read latency (default condition) t iaa hi-z ce clk avd oe rdy | | t rdys t rdya dq0: dq15 d6 d7 d0 d1 d2 d3 d7 d0 hi-z | | | | 0123 -1 t ba rising edge of the clock cycle following last read latency triggers next burst data a0: a15 valid address 4 3.9.3 4-, 8-, 16-, 32-, 1k- word linear burst read operation during synchronous burst block read mode
onenand2g(kfg2g16q2m-debx) flash memory 104 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the handshaking feature allows the host system to simply monitor the rdy signal from the device to determine when the initial w ord of burst data is ready to be read. to set the number of initial cycles for optimal burst mode, the host should use the programmable burst read latency configurati on (see section 2.8.19, "system configuration1 register"). the rising edge of rdy which is derived at one cycle prior of data fetch clock indicates the initial word of valid burst data. 3.9.5 handshaking operation during synchronous burst block read mode synchronous burst block read operation flow chart write dfs, fba of flash add: f100h dq=dfs*, fba start write fpa, fsa of flash add: f107h dq=fpa, fsa 1) write fpc of flash add: f104h dq=fpc write synchronous burst add=f220h dq=000ah block read command wait for int register or pin 3) low to high transition add: f241h dq[15]=int host reads data from dataram 0 4) wait for int register or pin 3) high to low transition add: f241h dq[15]=int host may operate another device while ce of onenand is disabled 5) wait for int register or pin 3) low to high transition add: f241h dq[15]=int wait for int register or pin 3) high to low transition add: f241h dq[15]=int host may operate another device while ce of onenand is disabled 5) wait for int register or pin 3) low to high transition add: f241h dq[15]=int finished reading final page set by fpc? yes read controller status register add: f240h dq[10]=1(error) synchronous burst block dq[10]=0? yes no read completed synchronous burst block read fail no finished reading final page set by fpc? yes host reads data from dataram 1 4) host reads data from dataram 0 4) no write bsa*, bsc of flash 1) add: f200h dq=bsa, bsc select dataram for ddp add: f101h dq=dbs* write 0 to int register or pin 2)3) add: f241h dq=0000h * dbs, dfs is for ddp note: 1) these registers must be set as bsa=1000, bsc=00 and fsa=00. 2) int auto mode is mandatory for sy nchronous burst bloc k read operation. 3) for the continuous synchronous burst block read, only int pin is availabe. for the other fixed num- ber of words linear burst block read, both int register and int pin are avilable. 4) while reading data from dataram, all normal synchronous bu rst read mode is su pported for the main area. 5) at this time, host should disable the ce of onenand in order to operate another device. even if host does not operate another device, ce should be disabled during int low.
onenand2g(kfg2g16q2m-debx) flash memory 105 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) burst mode operations enable high-speed synchronous read and write operations. burst operations consist of a multi-clock sequen ce that must be performed in an ordered fashion. after ce goes low, the address to access is latched on the next rising edge of clk that adv is low. during this first clock rising edge, we indicates whether the operation is going to be a read (we = high) or write (we = low). the size of a burst can be specified in the bl as either a fixed length or continuous. fixed-length bursts consist of 4, 8, 16, and 32 words. continuous burst write has the ability to start at a specified address and burst within the designated dataram. the l atency count stored in the brwl defines the number of clock cycles that elapse before the initial data value is transferred between th e pro- cessor and onenand device. the rdy output will be asserted as soon as a burst is initiated, and will be de-asserted to indicate when data is to be transfe rred into (or out of) the memory. the processor can access other devices without incurring the timing penalty of the initial latency for a new burst by suspending burst mode. bursts are suspended by stopping clk. clk can be stopped high or low. note that the rdy output will continue to be active, and as a result no other devices should directly share the rdy connection to the controller. to continue the burst sequence, clk is restarted after valid data is available on the bus. same as the normal burst mode, the latency is determined by the host based on the brwl bit setting in the system configuration 1 register. the default brwl is 4 latency cycles. at clock frequencies of 40mhz or lower, latency cycles can be reduced to 3, at fre- quency range from 40mhz to 67mhz, latency cycle should be over 4. and at 83mhz frequency, brwl should be set to 6. brwl can be set up to 7 latency cycles. 3.10 synchronous write(rm=1, wm=1) see timing diagram 6.10
onenand2g(kfg2g16q2m-debx) flash memory 106 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the program operation is used to program data from the on-chip bufferrams into the nand flash memory array. the device has two 2kb data buffers, each 1 page (2kb + 64b) in size. each page has 4 sectors of 512b each main area and 16b spare area. the device can be programmed in units of 1~4 sectors. the architecture of the datarams permits a simultaneous data-write operation from the host to one of data buffers and a program operation from the other data buffer to the nand flash array memory. refer to section 3.12.2, "write while program operation", for more information. 3.11 program operation see timing diagram 6.13 within a block, the pages must be programmed consecutively from the lsb (least significant bit) page of the block to msb (most sig- nificant bit) pages of the block. random page address programming is prohibited. from the lsb page to msb page data in: data (1) data (64) (1) (2) (3) (32) (64) data register page 0 page 1 page 2 page 31 page 63 ex.) random page program (prohibition) data in: data (1) data (64) (2) (32) (3) (1) (64) data register page 0 page 1 page 2 page 31 page 63 addressing for program operation : : : :
onenand2g(kfg2g16q2m-debx) flash memory 107 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) program operation flow diagram during the execution of the internal program routine, the host is not required to provide any further controls or timings. furt hermore, all commands, except a reset command, will be ignored. a reset during a program operation will cause data corruption at the cor re- sponding location. if a program error is detected at the completion of the internal program routine, map out the block, including the page in err or, and copy the target data to another block. an error is signaled if dq10 = "1" of controller status register(f240h) . data input from the host to the dataram can be done at any time during the internal program routine after "start" but before th e "write program command" is written. start data input write dfs*, fba of flash add: f100h dq=dfs*, fba write fpa, fsa of flash add: f107h dq=fpa, fsa select dataram for ddp 1) add: f101h dq=dbs* write data into dataram 2) add: dp dq=data-in program completed write program command add: f220h dq=0080h or 001ah completed? wait for int register low to high transition add: f241h dq[15]=int read controller status register add: f240h dq[10]=error dq[10]=0? program error yes no no yes * dbs, dfs is for ddp : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * write 0 to interrupt register 3) add: f241h dq=0000h write bsa, bsc of dataram add: f200h dq=bsa, bsc note 1) dbs must be set before data input. 2) data input could be done anywhere between "start" and "write program command". 3) write 0 to interrupt regist er step may be ignored when us ing int auto mode. refer to chapter 2.8.18.1
onenand2g(kfg2g16q2m-debx) flash memory 108 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the 2x program is an extension of program operation. since the device is equipped with two datarams, and two-plane nand flash memory array, these two component enables simultaneous program of 4kb. plane1 has only even blocks such as block0, block2, block4 while plane2 has only odd blocks such as block1, block3, block5. in normal program, two datarams can be utilized to use dual buffering scheme to enhance program performance. in 2x program, since 4kb data is to be programmed into nand flash array, dual-operation is implemented in another way; the 2x program and 2x cache program operations are only performed based on pair blocks which are consecutive. 1. 4kb data write from host to datarams. 2. 2x program command(007dh) issue. 3. 4kb data will be trasfered to each page buffer in two-plane nand flash array at the same time. 4. the data will be placed on same page of respective blocks. if the host wants to program data under 4 sector size, unwanted area to be programmed must be written to all 1s. (bsc must be set to 00, which is 4sectors.) although host only set fba(i.e. even block in plane1) and bsa (i.e. dataram0) for the first page to execute this operation, the sec- ond page data on dataram1 are programed onto an odd block in plane2 at the same time. if one of two consecutive blocks is mapped out by invalid block management, the remaining block must be used for normal program . this 2x program is also used for final 2x cache program. note that 2x program command cannot be performed on otp block and 1st block otp. page a 2) program 2) program dataram1 1) data write 1) data write dataram0 page b plane1 plane2 3.11.1 2x program operation see timing diagram 6.14 note) the page number of page a and page b is identical in different block. if page a is i th page of block 2j , page b must be i th page of block 2j+1 . (j=0,1,2,3...)
onenand2g(kfg2g16q2m-debx) flash memory 109 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 2x program operation flow diagram start data input write dfs*, fba of flash add: f100h dq=dfs*, fba 3) write fpa, fsa of flash add: f107h dq=fpa, fsa 4) select dataram for ddp 1) add: f101h dq=dbs* write data into dataram 2) add: dp dq=data-in program completed write 2x program command completed? wait for int register low to high transition add: f241h dq[15]=int read controller status register add: f240h dq[10]=error dq[10]=0? program error yes no no yes * dbs, dfs is for ddp : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * write 0 to interrupt register 5) add: f241h dq=0000h write bsa, bsc of dataram 4) add: f200h dq=bsa, bsc note 1) dbs must be set before data input. 2) data input could be done anywhere between "start" and "write program command". 3) fba must be an even block. 4) these registers must be set as bsa=1000, bsc=00 and fsa=00. 5) write 0 to interrupt register step may be ignored when using int auto mode. refer to chapter 2.8.18.1 add: f220h dq=007dh
onenand2g(kfg2g16q2m-debx) flash memory 110 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the 2x cache program operation is invented to accomplish continuous 2x program operation efficiently by hiding transferring tim e from dataram to page buffer. 1. 4kb data write from host to datarams. 2. 2x cache program command issue. this will turn int pin to busy state 1) , ongo bit sets to 1. (note that before issuing 2x cache program command, host should make sure that the target blocks are unlocked.) 3. 4kb data will be trasfered to each page buffer in two-plane nand flash array at the same time. 4. when this transfer operation is complete, progr amming into nand flash array will automatically start, and at the same time, int bit will turn to 1 to indicate that datarams are now ready to be written with next 4kb data. 5. when second 4kb is written to two datarams, another 2x cache program command is issued and int bit will go to 0 1) . note 1) this is for int auto mode, for int manual mode case, user should write 0 to int bit before issuing any command. if host wants to program data under 4 sector size, unwanted area to be programmed must be written to all 1s. (bsc must be set to 00, which is 4sectors.) when int bit goes to 1 after second data transfer from datarams to pafe buffers are complete, user may check the status regis ter to check the 2x program status. during 2x cache program, error bit shows the status of previous program operation. for the final 4kb program of 2x cache program scheme, host should issue 2x program command(007dh). when the final two pages are programmed, int bit will turn to 1 and ongo status bit - which indicates the overall 2x cache program ongoing statu s - will go to 0. at the completion of 2x cache program operation, error bit will show the pass/fail status overall status of 2x program, and plane1 previous[4] ~ plane2 current[1] bit will show where the error occured accordingly . note that 2x cache programm command cannot be performed on otp block and 1st block otp. page a 3) program 4) program dataram1 1) data write 2) data write 5) data write (during step 3 & 4 when int bit goes to 1) 6) data write (during step 3 & 4 when int bit goes to 1) dataram0 page b plane1 plane2 3.11.2 2x cache program operation see timing diagram 6.15 note) the page number of page a and page b is identical in different block. if page a is i th page of block 2j , page b must be i th page of block 2j+1 . (j=0,1,2,3...)
onenand2g(kfg2g16q2m-debx) flash memory 111 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) start write dfs, fba of flash add: f100h dq=dfs, fba 2) wait for int register add: f241h dq=8040h complete last 2plane pgm? yes map out no low to high transition write fpa, fsa of flash add: f107h dq=fpa, fsa 3) write bsa, bsc of flash 4) add: f200h dq=bsa, bsc write 0 to interrupt register 5) add: f241h dq=0000h write 2x cache pgm cmd add: f220h dq=007fh write fba of flash add: f100h dq=fba 2) write fpa, fsa of flash add: f107h dq=fpa, fsa 3) write bsa, bsc of flash 3) add: f200h dq=bsa, bsc write 0 to interrupt register 4) add: f241h dq=0000h write 2x cache pgm cmd add: f220h dq=007fh wait for int register add: f241h dq=8040h low to high transition dq[10]=0? yes write fba of flash add: f100h dq=fba 2) write fpa, fsa of flash add: f107h dq=fpa, fsa 3) write bsa, bsc of flash 3) add: f200h dq=bsa, bsc write 0 to interrupt register 4) add: f241h dq=0000h write 2x pgm cmd add: f220h dq=007dh wait for int register add: f241h dq=8040h low to high transition add: f240h dq[10]=error read controller status register add: f240h dq[10]=error read controller status register dq[10]=0? no no 2x cache program operation flow diagram : if program operation r esults in an error, map out the block including th e page in error and copy the target data to another block. * * dbs, dfs is for ddp note 1) dbs must be set before data input. 2) fba must be an even block. 3) these registers must be set as bsa=1000, bsc=00 and fsa=00. 4) write 0 to interrupt register step may be ignore d when using int auto mode. refer to chapter 2.8.18.1 . select dataram for ddp 1) add: f101h dq=dbs write data into dataram0,1 add: dataram dq=data(4kb) write data into dataram0,1 add: dataram dq=data(4kb) write data into dataram0,1 add: dataram dq=data(4kb)
onenand2g(kfg2g16q2m-debx) flash memory 112 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the 2x interleave cache program is available only on ddp. host can write data on a chip while programming another chip with th is operation. 2x interleave cache program is executed as following: 1. 4kb data are written from host to datarams in chip1. 2. 2x cache program command issue. this will turn int pin to busy state 1) , ongo bit sets to 1. (note that before issuing 2x cache program command, host should make sure that the target blocks are unlocked.) 3. 4kb data will be trasfered to each page buffer in two-plane nand flash array at the same time. 4. while these data are transferring, host can write another 4kb data to dataram in chip2. 5. when the transfer operation is completed, programming into nand flash array will automatically start, and at the same time, int bit will turn to 1 to indicate that datarams are now ready to be written with next 4kb data. 6. second 4kb is writable on chip1 when int1 goes to 1. 7. when second 4kb is written to two datarams of chip1, another 2x cache program command is issued and int1 bit will go to 0 1) again. note 1) this is for int auto mode, for int manual mode case, user should write 0 to int bit before issuing any command. when int bit goes to 1 after second data transfer from datarams to page buffers are completed, user may check the status reg- ister to check the 2x program status. during 2x cache program, plane1/2 previous bit shows the status of previous program opera - tion. for the final 4kb program of 2x interleave cache program scheme, host should issue 2x program command(007dh) on each chip. if the host issues 007dh on only a chip, another chip will be on operation as it isnt finished. ongo status bit will show the ongoing sta- tus of each chip. its operation is same as 2x cache program operation on each chip. error bit will show the pass/fail status of each chip of 2x interleave cache program, and plane1 previous[4] ~ plane2 current[1] bit will show where the error occured according ly . note that otp block and 1st block otp cannot be 2x interleave cache programmed. page a 2) program 2) program dataram1 1) data write 1) data write 5) data write (during step 4) when int1 bit goes to 1) 5) data write dataram0 page b plane1 plane2 page a 4) program 4) program dataram1 3) data write dataram0 page b plane1 plane2 chip2 chip1 (during step 4) when int1 bit goes to 1) (during step 2) when int2 bit is on 1) 3) data write (during step 2) when int2 bit is on 1) 3.11.3 2x interleave cache program operation see timing diagram 6.16
onenand2g(kfg2g16q2m-debx) flash memory 113 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 2x interleave cache program operation flow diagram start write dfs, fba of flash add: f100h dq=dfs, fba 2) select dataram for ddp 1) add: f101h dq=dbs check int register add: f241h dq=8040h complete map out if it is ready 5) write fpa, fsa of flash add: f107h dq=fpa, fsa 3) write bsa, bsc of flash 3) add: f200h dq=bsa, bsc write data into dataram0,1 add: dataram dq=data(4kb) write 2x cache pgm cmd add: f220h dq=007fh add: f240h read controller status register is it first input for a chip select dataram for ddp 1) add: f101h dq=dbs dq[4] | dq[2] = 0? last 2 plane pgm for a chip? write dfs, fba of flash add: f100h dq=dfs, fba 2) write fpa, fsa of flash add: f107h dq=fpa, fsa 3) write bsa, bsc of flash 3) add: f200h dq=bsa, bsc write data into dataram0,1 add: dataram dq=data(4kb) write 2x pgm cmd 6) add: f220h dq=007dh write dfs, fba of flash add: f100h dq=dfs, fba 2) write fpa, fsa of flash add: f107h dq=fpa, fsa 3) write bsa, bsc of flash 3) add: f200h dq=bsa, bsc write data into dataram0,1 add: dataram dq=data(4kb) write 2x pgm cmd 6) add: f220h dq=007dh select dataram for ddp 1) add: f101h dq=dbs check int register add: f241h dq=8040h if it is ready 5) dq[4] | dq[2] = 0? dq[10]=0? wait for int register add: f241h dq=8040h low to high transition 4) add: f240h dq[10]=error read controller status register 7) select dataram for ddp 1) add: f101h dq=dbs check int register add: f241h dq=8040h if it is ready 5) dq[10]=0? add: f240h dq[10]=error read controller status register 7) yes no yes yes no no yes no yes no yes no * dbs, dfs is for ddp note 1) dbs must be set before data input. 2) fba must be an even block. 3) these registers must be set as bsa=1000, bsc=00 and fsa=00. 4) write 0 to interrupt register step may be ignored when using int auto mode. refer to chapter 2.8.18.1 . 5) host is strongly recommended to see the int register(f241h) of each chip. 6) once 2x pgm command is issued onto a chip, the same command(2x pgm) must be issued onto another chip. if not, samsung can not gurantee the following operation. 7) if error bit is set at this step, dq[1]~[4] shoulde be checked in order to find where the error occurred. * if program operation results in an error, map out the block including the page in error and copy the target data to another block. dq[4],[2]=plane1,2 previous add: f240h read controller status register dq[4],[2]=plane1,2 previous write 0 to interrupt register 4) add: f241h dq=0000h write 0 to interrupt register 4) add: f241h dq=0000h write 0 to interrupt register 4) add: f241h dq=0000h
onenand2g(kfg2g16q2m-debx) flash memory 114 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the copy-back program is configured to quickly rewrite data stored in one page without utilizing memory other than onenand. since the time-consuming cycles of serial access and re-loading cycles are removed, the system performance is improved. the ben - efit is especially obvious when a portion of block is updated and the rest of the block also need to be copied to the newly ass igned free block. data from the source page is saved in one of the on-chip dataram buffers and then programmed directly into the destination page . the dataram is overwritten the previous data using the buffer sector address (bsa) and buffer sector count (bsc). the copy-back program operation does this by performing sequential page-reads without a serial access and executing a copy-program using the address of the destination page. in ddp, copy-back program must be executed within each chip. copy-back program operation flow chart note 1) selected dataram by bsa & bsc is used for copy back operation, so previous data is overwritten. 2) fba, fpa and fsa should be input prior to fcba, fcpa and fcsa. 3.12 copy-back program operation 3) write 0 to interrupt register step may be ignor ed when using int auto mode. refer to chapter 2.8.18.1 start write dfs*, fba of flash add: f100h dq=dfs*, fba write fpa, fsa of flash add: f107h dq=fpa, fsa write fcba of flash add: f102h dq=fcba write fcpa, fcsa of flash add: f103h dq=fcpa, fcsa copy back completed write copy-back program command add: f220h dq=001bh wait for int register low to high transition add: f241h dq[15]=int read controller status register add: f240h dq[10]=error dq[10]=0? copy back error yes no * dbs, dfs is for ddp : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * select dataram for ddp add: f101h dq=dbs* write 0 to interrupt register add: f241h dq=0000h write bsa, bsc of dataram add: f200h dq=bsa, bsc 1)
onenand2g(kfg2g16q2m-debx) flash memory 115 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the copy-back steps shown in the flow chart are: x data is read from the nand array using flash block address (fba), flash page address (fpa) and flash sector address (fsa). fba, fpa, and fsa identify the source address to read data from nand flash array. x the bufferram sector count (bsc) and bufferram sector address (bsa) identifies how many sectors and the location of the sectors in dataram that are used. x the destination address in the nand array is written using the flash copy-back block address (fcba), flash copy-back page address (fcpa), and flash copy-back sector address (fcsa). x the copy-back program command is issued to start programming. x upon completion of copy-back programming to the destination page address, the host checks the status to see if the operation was successfully completed. if there was an error, map out the block including the page in error and copy the target data to another block.
onenand2g(kfg2g16q2m-debx) flash memory 116 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the copy-back program operation with random data input in onenand consists of 2 phase, load data into dataram, modify data and program into designated page. data from the source page is saved in one of the on-chip dataram buffers and modified by the host, then programmed into the destination page. as shown in the flow chart, data modification is possible upon completion of load operation. ecc is also available at the end o f load operation. therefore, using hardware ecc of onenand, accumulation of 1 bit error can be avoided. copy-back program operation with random data input will be effectively utilized at modifying certain bit, byte, word, or sector of source page to destination page while it is being copied. copy-back program operation with random data input flow chart 3.12.1 copy-back program operation with random data input start write dfs*, fba of flash add: f100h dq=dfs, fba write fpa, fsa of flash add: f107h dq=fpa, fsa write bsa, bsc of dataram add: f200h dq=bsa, bsc select dataram for ddp add: f101h dq=dbs write load command add: f220h dq=0000h or 0013h wait for int register low to high transition add: f241h dq[15]=int read controller add: f240h dq[10]=error dq[10]=0? no yes * dbs, dfs is for ddp status register map out write 0 to interrupt register 1) add: f241h dq=0000h copy back completed wait for int register low to high transition add: f241h dq[15]=int read controller status register add: f240h dq[10]=error dq[10]=0? copy back error yes no random data input write fba of flash add: f100h dq=fba write fpa, fsa of flash add: f107h dq=fpa, fsa write program command add: f220h dq=0080h or 001ah write 0 to interrupt register 1) add: f241h dq=0000h add: random address in selected dataram dq=data note 1) write 0 to interrupt register step may be ignored when using int auto mode. refer to chapter 2.8.18.1
onenand2g(kfg2g16q2m-debx) flash memory 117 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) there are multiple methods for erasing data in the device including block erase and multi-block erase. 3.13.1 block erase operation see timing diagram 6.17 the block erase operation is done on a block basis. to erase a block is to write all 1's into the desired memory block by execu ting the internal erase routine. all previous data is lost. block erase operation flow chart 3.13 erase operation start write dfs*, fba of flash add: f100h dq=dfs*, fba write erase command add: f220h dq=0094h wait for int register add: f241h dq=[15]=int add: f240h dq[10]=error erase completed dq[10]=0? yes erase error no low to high transition read controller status register : if erase operation resu lts in an error, map out the failing block and replace it with another block. * write 0 to interrupt register 1) add: f241h dq=0000h * dbs, dfs is for ddp note 1) write 0 to interrupt register step may be ignored when using int au to mode. refer to chapter 2.8.18.1 select dataram for ddp add: f101h dq=dbs*
onenand2g(kfg2g16q2m-debx) flash memory 118 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) in order to perform the internal erase routine, the following command sequence is necessary. x the host selects flash core of ddp chip. x the host sets the block address of the memory location. x the erase command initiates the internal erase routine. during the execution of the routine, the host is not required to provide further controls or timings. during the internal erase routine, all commands, except the reset command and erase suspend command, written to the device will be ignored. a reset during an erase operation will cause data corruption at the corresponding location. using multi-block erase, the device can be erased up to 64 multiple blocks simultaneously. multiple blocks can be erased by issuing a multi-block erase command and writing the block address of the memory location to be erased. the final flash block address (fba) and block erase command initiate the internal multi block era se routine. during a multi-block erase, the ongo bit of the controller status register is set to '1'(busy) from the time that the first block addres s to be latched is written to the time that the actual erase operation finishes. during block address latch sequence, issuing of other commands except block erase, and multi block erase at int=high will abort the current operation. so to speak, it will cancel the previously latched addresses of multi block erase operation. on the other hand, other command issue at int=low will be ignored. a reset during an erase operation will cause data corruption at the address location being operated on during the reset. despite a failed block during multi-block erase operation, the device will continue the erase operation until all other specifi ed blocks are erased. erase suspend command issue during multi block erase address latch sequence is prohibited. locked blocks if there are locked blocks in the specified range, the multi-block erase operation works as the follows. case 1: all specified blocks except ba(2) will be erased. [ba(1)+0095h] + [ ba((2), locked)) +0095h] + ... + [ba(n-1)+0095h] + [ba(n)+0094h] case 2: multi-block erase operation fails to start if the last block erase command is put together with the locked block addres s until right command and address input are issued. [ba(1)+0095h] + [ba(2)+0095h] + ... + [ba(n-1)+0095h] + [ ba((n), locked) +0094h] case 3: all specified blocks except ba(n) are erased. 3.13.2 multi-block erase operation see timing diagram 6.17
onenand2g(kfg2g16q2m-debx) flash memory 119 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) after a multi-block erase operation, verify erase operation result of each block with multi-block erase verify command combined with address of each block. if a failed address is identified, it must be managed by firmware. 3.13.3 multi-block erase verify read operation multi block erase/ multi block erase verify read flow chart start write dfs 1) , fba of flash add: f100h dq=dfs, fba write multi block erase add: f220h dq=0095h wait for int register add: f241h dq=[15]=int final multi block yes no low to high transition write 0 to interrupt register 2) add: f241h dq=0000h command erase? write fba of flash add: f100h dq=fba write block erase add: f220h dq=0094h wait for int register add: f241h dq=[15]=int low to high transition write 0 to interrupt register 2) add: f241h dq=0000h command multi block erase verify read write fba of flash add: f100h dq=fba write multi block erase add: f220h dq=0071h wait for int register add: f241h dq=[15]=int low to high transition write 0 to interrupt register 2) add: f241h dq=0000h verify read command read controller add: f240h dq[10]=error status register dq[10]=0? multi block erase completed final multi block yes no erase address? erase completed yes erase error no *dbs, dfs is for ddp note 1) dfs should be a fixed value, for multi block erase is performed within a single chip. 2) write 0 to interrupt register step may be ign ored when using int auto mode. refer to chapter 2.8.18.1 select dataram for ddp add: f101h dq=dbs*
onenand2g(kfg2g16q2m-debx) flash memory 120 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the erase suspend/erase resume commands interrupt and restart a block erase or multi-block erase operation so that user may perform another urgent operation on the block that is not being designated by erase/multi-block erase operation. erase suspend during a block erase operation when erase suspend command is written during a block erase or multi-block erase operation, the device requires a maximum of 500us to suspend erase operation. erase suspend command issue during block address latch sequence is prohibited. after the erase operation has been suspended, the device is ready for the next operation including a load, program, copy-back program, lock, unlock, lock-tight, hot reset, nand flash core reset, command based reset, multi-block erase read verify, or otp access. the subsequent operation can be to any block that was not being erased. a special case arises pertaining erase suspend to the otp. a reset command is used to exit from the otp access mode. if the reset-triggered exit from the otp access mode happens during an erase suspend operation, the erase routine could fail. therefor e to exit from the otp access mode without suspending the erase operation stop, a 'nand flash core reset' command should be issued. for the duration of the erase suspend period the following commands are not accepted: x block erase/multi-block erase/erase suspend 3.13.4 erase suspend / erase resume operation erase suspend and erase resume operation flow chart start write erase suspend add: f220h dq=00b0h wait for int register add: f241h dq=[15]=int low to high transition for 500us command 1) write 0 to interrupt register 3) add: f241h dq=0000h write erase resume add: f220h dq=0030h wait for int register add: f241h dq=[15]=int low to high transition write 0 to interrupt register 3) add: f241h dq=0000h command another operation * * another operation ; load, program copy-back program, otp access 2) , hot reset, flash reset, cmd reset, multi block erase verify, lock, lock-tight, unlock check controller status register do multi block erase verify read in case of block erase in case of multi block erase 2) if otp access mode exit happens with reset operation during erase suspend mode, reset operation could hurt the erase operation. so if a user wants to exit from otp access mode without the erase operation stop, reset nand flash core command should be used. note 1) erase suspend command input is prohibited during multi block erase address latch period. 3) write 0 to interrupt register step may be ignored when using int auto mode. refer to chapter 2.8.18.1 select dataram for ddp add: f101h dq=dbs** write dfs of flash add: f100h dq=dfs** select dataram for ddp add: f101h dq=dbs** ** dbs, dfs is for ddp
onenand2g(kfg2g16q2m-debx) flash memory 121 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) erase resume when the erase resume command is executed, the block erase will restart. the erase resume operation does not actually resume the erase, but starts it again from the beginning. when an erase suspend or erase resume command is executed, the addresses are in don't care state. for multi block erase, erase suspend/resume can be operated after final erase command (0094h) is issued. therefore, erase resume operation does not actually resume from the erased block, but resumes the multi block erase from the beginning. one block of the nand flash array memory is reserved as a one-time programmable block memory area. also, 1st block of nand flash array can be used as otp. the otp block can be read, programmed and locked using the same operations as any other nand flash array memory block. otp block cannot be erased. note that 2x program and 2x cache program command cannot be perfomed on otp and 1st block otp area. otp block is fully-guaranteed to be a valid block. entering the otp block the otp block is separately accessible from the rest of the nand flash array by using the otp access command instead of the flash block address (fba). exiting the otp block to exit the otp access mode, a cold-, warm-, hot-, or nand flash core reset operation is performed. exiting the otp block during an erase operation if the reset-triggered exit from the otp access mode happens during an erase suspend operation, the erase routine could fail. therefore to exit from the otp access mode without suspending the erase operation stop, a 'nand flash core reset' command should be issued. the otp block page assignments otp area is one block size (128kb+4kb, 64 pages) and is divided into two areas. the 50-page user area is available as an otp storage area. the 14-page manufacturer area is programmed by the manufacturer prior to shipping the device to the user. otp block page allocation information three possible otp lock sequence (refer to chapter 3.14.3~3.14.5 for more information) since otp block and 1st block otp can be locked only by programming into 8th word of sector0, page0 of the spare memory area of otp, otp block and 1st block otp lock sequence is restricted into three following cases. note that user should be careful, because locking otp block before locking 1st block otp will disable locking 1st block otp. 1. otp block lock only : once the otp block is locked, 1st block otp lock is impossible. 2. 1st block otp lock, and then lock otp block afterwards : locking 1st block otp does not lock the otp block, so that otp block lock can be performed thereafter. 3. otp block lock and 1st block otp lock simultaneously: this simultaneous operation can be done by programming into 8th word of sector0, page0 of the spare memory area o f otp. area page use user 0 ~ 49 (50 pages) designated as user area manufacturer 50 ~ 63 (14 pages) used by the device manufacturer 3.14 otp operation
onenand2g(kfg2g16q2m-debx) flash memory 122 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) otp block area structure 1st block otp area structure page:2kb+64b sector(main area):512b sector(spare area):16b one block: 128kb+4kb 64pages user area : page 0 to page 63 64pages page:2kb+64b sector(main area):512b sector(spare area):16b one block: 128kb+4kb 64pages manufacturer area : page 50 to page 63 14pages user area : page 0 to page 49 50pages
onenand2g(kfg2g16q2m-debx) flash memory 123 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) an otp block load operation accesses the otp area and transfers identified content from the otp to the dataram on-chip buffer, thus making the otp contents available to the host. the otp area is a separate part of the nand flash array memory. it is accessed by issuing otp access command(65h) instead of a flash block address (fba) command. after being accessed with the otp access command, the contents of otp memory area are loaded using the same operations as a normal load operation to the nand flash array memory (see section 3.6 for more information). to exit the otp access mode following an otp block load operation, a cold-, warm-, hot-, or nand flash core reset operation is performed. otp block read operation flow chart note 1) fba(nand flash block address) could be omitted or any address. 3.14.1 otp block load operation 2) write 0 to interrupt register step may be igno red when using int auto mode. refer to chapter 2.8.18.1 start wait for int register add: f241h dq[15]=int write 0 to interrupt register 2) add: f241h dq=0000h write fpa, fsa of flash add: f107h dq=fpa, fsa otp reading completed write load command add: f220h dq=0000h or 0013h wait for int register low to high transition add: f241h dq[15]=int write otp access command add: f220h dq=0065h write bsa, bsc of dataram add: f200h dq=bsa, bsc low to high transition otp exit host reads data from dataram do cold/warm/hot /nand flash core reset * dbs, dfs is for ddp write dfs*, fba of flash 1) add: f100h dq=dfs*, fba write 0 to interrupt register 2) add: f241h dq=0000h select dataram for ddp add: f101h dq=dbs*
onenand2g(kfg2g16q2m-debx) flash memory 124 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) an otp block program operation accesses the otp area and programs content from the dataram on-chip buffer to the designated page(s) of the otp. a memory location in the otp area can be programmed only one time (no erase operation permitted). the otp area is programmed using the same sequence as normal program operation after being accessed by the command (see section 3.8 for more information). programming the otp area x issue the otp access command x write data into the dataram (data can be input at anytime between the "start" and "write program" commands x issue a flash block address (fba) which is unlocked area address of nand flash array address map. x issue a write program command to program the data from the dataram into the otp x when the otp block programming is complete, do a cold-, warm-, hot-, nand flash core reset to exit the otp access mode. 3.14.2 otp block program operation
onenand2g(kfg2g16q2m-debx) flash memory 125 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) otp block program op eration flow chart select dataram for ddp add: f101h dq=dbs* write dfs*, fba of flash 1) add: f100h dq=dfs*, fba start data input write otp access command add: f220h dq=0065h write fpa, fsa of flash add: f107h dq=fpa, fsa write bsa, bsc of dataram add: f200h dq=bsa, bsc write data into dataram 2) add: dp dq=data-in otp programming completed write program command dq=0080h or 001ah completed? wait for int register low to high transition add: f241h dq[15]=int no add: f220h wait for int register add: f241h dq[15]=int write 0 to interrupt register 4) add: f241h dq=0000h low to high transition do cold/warm/hot otp exit automatically checked wait for int register low to high transition add: f241h dq[15]=int otp exit automatically otp l =0? yes no updated read controller status register add: f240h dq[10]=1(error) add: f200h dq=bsa, bsc write fba of flash add: f100h dq=fba 3) read controller status register add: f240h dq[10]=0(pass) /nand flash core reset do cold/warm/hot /nand flash core reset write 0 to interrupt register 4) add: f241h dq=0000h * dbs, dfs is for ddp note 1) fba(nand flash block address) could be omitted or any address. 2) data input could be done anywhere between "start" and "write program command". 3) fba should point the unlocked area address among nand flash array address map. 4) write 0 to interrupt register step may be ignored when using int auto mode. refer to chapter 2.8.18.1 update controller add: f240h status register dq[14]=1(lock), dq[10]=1(error)
onenand2g(kfg2g16q2m-debx) flash memory 126 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) even though the otp area can only be programmed once without erase capability, it can be locked when the device starts up to pr e- vent any changes from being made. unlike the main area of the nand flash array memory, once the otp block is locked, it cannot be unlocked, for locking bit for both blocks lies in the same word of otp area. therefore, if otp block is locked prior to 1st block otp lock, 1st block otp cannot be locked. locking the otp programming to the otp area can be prevented by locking the otp area. locking the otp area is accomplished by programming xxfch to 8th word of sector0 in page0 spare area in the otp block. at device power-up, this word location is checked and if xxfch is found, the otp l bit of the controller status register is set to "1", indicating the otp is locked. when the program operation finds that the status of the otp is locked, the device updates the err or bit of the controller status register as "1" (fail). otp lock operation steps x issue the otp access command x fill data to be programmed into dataram (data can be input at anytime between the "start" and "write program" commands) x write ' xxf3h ' data into the 8th word of sector0 in page0 spare area of the dataram. x issue a flash block address (fba) which is unlocked area address of nand flash array address map. x issue a program command to program the data from the dataram into the otp x when the otp lock is complete, do a cold reset to exit the otp access mode and update otp lock bit[6]. x otp lock bit[6] of the controller status register will be set to "1" and the otp will be locked. 3.14.3 otp block lock operation
onenand2g(kfg2g16q2m-debx) flash memory 127 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) otp block lock operation flow chart start write fpa, fsa of flash add: f107h dq=0000h write bsa, bsc of dataram add: f200h dq=0801h/0c01h write data into dataram 2) add: 8th word write program command dq=0080h or 001ah wait for int register low to high transition add: f241h dq[15]=int add: f220h write 0 to interrupt register 4) add: f241h dq=0000h automatically updated dq=xxfch in sector0/spare/page0 otp lock completed write fba of flash add: f100h dq=fba 3) write otp access command add: f220h dq=0065h wait for int register add: f241h dq[15]=int low to high transition write 0 to interrupt register 4) add: f241h dq=0000h do cold reset write dfs, fba of flash 1) add: f100h dq=dfs, fba select dataram for ddp add: f101h dq=dbs* * dbs, dfs is for ddp note 1) fba(nand flash block address) could be omitted or any address. 2) data input could be done anywhere between "start" and "write program command". 3) fba should point the unlocked area address among nand flash array address map. 4) write 0 to interrupt register step may be ignored when using int auto mode. refer to chapter 2.8.18.1 update controller add: f240h status register dq[14]=1(lock), dq[10]=1(error)
onenand2g(kfg2g16q2m-debx) flash memory 128 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 1st block could be used as otp, for secured booting operation. 1st block otp can be accessed just as any other nand flash array blocks before it is locked, however, once 1st block is locked to be otp, 1st block otp cannot be erased or programmed. note that otp block can be locked freely after locking 1st block otp. locking the 1st block otp programming to the 1st block otp area can be prevented by locking the otp area. locking the otp area is accomplished by programming xxf3h to 8th word of sector0 in page0 spare area in the otp block. at device power-up, this word location is checked and if xxf3h is found, the otp bl bit of the controller status register is set to "1", indicating the 1st block is locked. when the program operation finds that the status of the 1st block is locked, the device upd ates the error bit of the controller status register as "1" (fail). 1st block otp lock operation steps x issue the otp access command x fill data to be programmed into dataram (data can be input at anytime between the "start" and "write program" commands) x write ' xxf3h ' data into the 8th word of sector0 in page0 spare area of the dataram. x issue a flash block address (fba) which is unlocked area address of nand flash array address map. x issue a program command to program the data from the dataram into the otp x when the 1st block otp lock is complete, do a cold reset to exit the otp access mode and update 1st block otp lock bit[5]. x 1st block otp lock bit[5] of the controller status register will be set to "1" and the 1st block will be locked. even though the otp area can only be programmed once without erase capability, it can be locked when the device starts up to pr e- vent any changes from being made. unlike other remaining main area of the nand flash array memory, once the 1st block otp is locked, it cannot be unlocked. 3.14.4 1st block otp lock operation
onenand2g(kfg2g16q2m-debx) flash memory 129 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 1st block otp lock operation flow chart start write fpa, fsa of flash add: f107h dq=0000h write bsa, bsc of dataram add: f200h dq=0801h/0c01h write data into dataram 2) add: 8th word write program command dq=0080h or 001ah wait for int register low to high transition add: f241h dq[15]=int add: f220h write 0 to interrupt register 4) add: f241h dq=0000h automatically updated dq=xxf3h in sector0/spare/page0 1st block otp lock completed write fba of flash add: f100h dq=fba 3) write otp access command add: f220h dq=0065h wait for int register add: f241h dq[15]=int low to high transition write 0 to interrupt register 4) add: f241h dq=0000h do cold reset write dfs, fba of flash 1) add: f100h dq=dfs, fba select dataram for ddp add: f101h dq=dbs* * dbs, dfs is for ddp note 1) fba(nand flash block address) could be omitted or any address. 2) data input could be done anywhere between "start" and "write program command". 3) fba should point the unlocked area address among nand flash array address map. 4) write 0 to interrupt register step may be ignored when using int auto mode. refer to chapter 2.8.18.1 update controller add: f240h status register dq[14]=1(lock), dq[10]=1(error)
onenand2g(kfg2g16q2m-debx) flash memory 130 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) otp and 1st block can be locked simultaneously, for locking bit lies in the same word of otp area. 1st block otp can be accessed just as any other nand flash array blocks before it is locked, however, once 1st block is locked to be otp, 1st block otp cannot be erased or programmed. also, otp area can only be programmed once without erase capability, it can be locked when the device starts up to prevent any changes from being made. locking the otp and 1st block otp programming to the otp area and 1st block otp area can be prevented by locking the otp area. locking the otp area is accomplished by programming xxf0h to 8th word of sector0 in page0 spare area in the otp block. at device power-up, this word location is checked and if xxf0h is found, the otp l and otp bl bit of the controller status register is set to "1", indicating the otp and 1st block is locked. when the program operation finds that the status of the otp and 1st blo ck is locked, the device updates the error bit of the controller status register as "1" (fail). otp and 1st block otp simultaneous lock operation steps x issue the otp access command x fill data to be programmed into dataram (data can be input at anytime between the "start" and "write program" commands) x write 'xxf0h' data into the 8th word of sector0 in page0 spare area of the dataram. x issue a flash block address (fba) which is unlocked area address of nand flash array address map. x issue a program command to program the data from the dataram into the otp x when the 1st block otp lock is complete, do a cold reset to exit the otp access mode and update 1st block otp lock bit[5] and otp lock bit[6]. x 1st block otp lock bit[5] and otp lock bit[6] of the controller status register will be set to "1" and the otp and 1st block will be locked. even though the otp area can only be programmed once without erase capability, it can be locked when the device starts up to pr e- vent any changes from being made. unlike other remaining main area of the nand flash array memory, once the otp block and the 1st block otp are locked, it cannot be unlocked. 3.14.5 otp and 1st block otp lock operation
onenand2g(kfg2g16q2m-debx) flash memory 131 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) otp and 1st block otp lock operation flow chart start write fpa, fsa of flash add: f107h dq=0000h write bsa, bsc of dataram add: f200h dq=0801h/0c01h write data into dataram 2) add: 8th word write program command dq=0080h or 001ah wait for int register low to high transition add: f241h dq[15]=int add: f220h write 0 to interrupt register 4) add: f241h dq=0000h automatically updated dq=xxf0h in sector0/spare/page0 otp and 1st block otp lock completed write fba of flash add: f100h dq=fba 3) write otp access command add: f220h dq=0065h wait for int register add: f241h dq[15]=int low to high transition write 0 to interrupt register 4) add: f241h dq=0000h do cold reset write dfs, fba of flash 1) add: f100h dq=dfs, fba select dataram for ddp add: f101h dq=dbs* * dbs, dfs is for ddp note 1) fba(nand flash block address) could be omitted or any address. 2) data input could be done anywhere between "start" and "write program command". 3) fba should point the unlocked area address among nand flash array address map. 4) write 0 to interrupt register step may be ignored when using int auto mode. refer to chapter 2.8.18.1 update controller add: f240h status register dq[14]=1(lock), dq[10]=1(error)
onenand2g(kfg2g16q2m-debx) flash memory 132 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the device has independent dual data buffers on-chip (except during the boot load period) that enables higher performance read and program operation. 3.15.1 read-while-load operation this operation accelerates the read performance of the device by enabling data to be read out by the host from one dataram buff er while the other dataram buffer is being loaded with data from the nand flash array memory. page a page b 1) data load 2) data load data buffer1 data buffer0 2) data read 3) data read 3) data load the dual data buffer architecture provides the capability of executing a data-read operation from one of dataram buffers during a simultaneous data-load operation from flash to the other buffer. simultaneous load and read operation to same data buffer is prohibited. see sections 3.6 and 3.7 for more information on load and read operations. if host sets fba, fsa, or fpa while loading into designated page, it will fail the internal load operation. address registers should not be updated until internal operation is completed. this operation accelerates the programming performance of the device by enabling data to be written by the host into one datara m buffer while the nand flash array memory is being programmed with data from the other dataram buffer. page a page b 2) program 3) program data buffer1 data buffer0 1) data write 2) data write 3) data write the dual data buffer architecture provides the capability of executing a data-write operation to one of dataram buffers during simul- taneous data-program operation to flash from the other buffer. simultaneous program and write operation to same data buffer is prohibited. see sections 3.8 for more information on program operation. if host sets fba, fsa, or fpa while programming into designated page, it will fail the internal program operation. address reg isters should not be updated until internal operation is completed. 3.15 dual operations 3.15.2 write-while-program operation
onenand2g(kfg2g16q2m-debx) flash memory 133 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) read while load diagram page b add we oe int 0~15 2) 2) page a 1) add_ reg int_ reg cmd_ reg cs_ reg data load _db0 data load _db1 data read _db0 * add_ reg int_ reg cmd_ reg add_ reg add_ reg db1 _add ld_ cmd read status db0 _add 0000h ld_ cmd flash dq 0~15 int_reg : interrupt register address add_reg : address register address flash_add : flash address to be loaded dbn_add : dataram address to be loaded cmd_reg : command register address ld_cmd : load command data load_dbn : load data from nand flash array to dataramn cs_reg : controller status register address data read_dbn : read data from dbn dbn_radd : dataram address to be read 1) data load _db0 db0_radd* data load _db1 _add 0000h flash _add * dbs should be set before accessing dataram for ddp
onenand2g(kfg2g16q2m-debx) flash memory 134 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) write while program diagram page b add oe int 0~15 page a 1) we db0_wadd* add_ reg add_ reg int_ reg cmd_ reg cs_ reg int_ reg cmd_ reg data pgm _pageb dq 0~15 db0 _add flash _add 0000h pd_ cmd data write _db1 * db1 _add read status 0000h pd_ cmd data pgm _pagea add_reg : address register address dbn_add : dataram address to be programmed dbn_wadd : dataram address to be written data write_dbn : write data to dataramn flash_add : flash address to be programmed int_reg : interrupt register address cmd_reg : command register address pd_cmd : program command data pgm_pagea : program data from dataram to pagea cs_reg : controller status register address data write _db0 * db1_wadd* data pgm _pagea 2) add_ reg add_ reg flash _add data write _db0 * db0_wadd* data pgm _pageb * dbs should be set before accessing dataram for ddp
onenand2g(kfg2g16q2m-debx) flash memory 135 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) the onenand device has on-chip ecc with the capability of detecting 2 bit errors and correcting 1-bit errors in the nand flash array memory main and spare areas. as the device transfers data from a bufferram to the nand flash array memory page buffer for program operation, the device ini- tiates a background operation which generates an error correction code (ecc) of 24bits for each sector main area data and 10bit s for 2nd and 3rd word data of each sector spare area. during a load operation from the nand flash array memory page, the on-chip ecc engine generates a new ecc. the 'load ecc result' is compared to the originally 'program ecc' thus detecting the number and position of errors. single-bit error is corre cted. ecc is updated by the device automatically. after a load operation, the host can determine whether there was error by reading t he 'ecc status register' (refer to section 2.8.26). error types are divided into 'no error', '1bit correctable error', and '2bit error uncorrectable error'. onenand supports 2bit edc even though 2bit error seldom or never occurs. hence, it is not recommended for host to read 'ecc status register' for checking ecc error because the built-in error correction logic of onenand automatically corrects ecc error . when the device reads the nand flash array memory main and spare area data with an ecc operation, the device doesn't place the newly generated ecc for main and spare area into the buffer. instead it places the ecc which was generated and written duri ng the program operation into the buffer. an ecc operation is also done during the boot loading operation. in an ecc bypass operation, the device does not generate ecc as a background operation. the result does not indicate error posi - tion (refer to the ecc result table). in a program operation the ecc code to nand flash array memory spare area is not updated. during a load operation, the on-chip ecc engine does not generate a new ecc internally. also the ecc status & result to regis- ters are invalid. the error is not corrected and detected by itself, so that ecc bypass operation is not recommended for host. ecc bypass operation is set by the 9bit of system configuration 1 register (see section 2.8.19) ecc code and ecc result by ecc operation note: 1. pre-written ecc code : ecc code which is previously written to nand flash spare area in program operation. operation program operation load operation ecc code update to nand flash array spare area ecc code at bufferram spare area ecc status & result update to registers 1bit error ecc operation update pre-written ecc code (1) loaded update correct ecc bypass not update pre-written code (1) loaded invalid not correct 3.16 ecc operation 3.16.1 ecc bypass operation
onenand2g(kfg2g16q2m-debx) flash memory 136 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) invalid blocks are defined as blocks in the device's nand flash array memory that contain one or more invalid bits whose reliab ility is not guaranteed by samsung. the information regarding the invalid block(s) is called the invalid block information. devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same ac and dc characteristics. an invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common s ource line by a select transistor. the system design must be able to mask out the invalid block(s) via address mapping. the 1st block, which is placed on 00h bloc k address, is always fully guaranteed to be a valid block. due to invalid marking, during load operation for indentifying invalid block, a load error may occur. 3.17.1 invalid block identification table operation a system must be able to recognize invalid block(s) based on the original invalid block information and create an invalid block table. invalid blocks are identified by erasing all address locations in the nand flash array memory except locations where the invali d block(s) information is written prior to shipping. an invalid block(s) status is defined by the 1st word in the spare area. samsung makes sure that either the 1st or 2nd page of every invalid block has non-ffffh data at the 1st word of sector0. since the invalid block information is also erasable in most cases, it is impossible to recover the information once it has bee n erased. any intentional erase of the original invalid block information is prohibited. the following suggested flow chart can be used to create an invalid block table. 3.17 invalid block operation
onenand2g(kfg2g16q2m-debx) flash memory 137 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) invalid block table creation flow chart within its life time, additional invalid blocks may develop with nand flash array memory. refer to the device's qualification r eport for the actual data. the following possible failure modes should be considered to implement a highly reliable system. in the case of a status read failure after erase or program, a block replacement should be done. because program status failure during a page program does not affect the data of the other pages in the same block, a block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replac ed block. block failure modes and countermeasures failure mode detection and countermeasure sequence erase failure status read after erase --> block replacement program failure status read after program --> block replacement single bit failure in load operation error correction by ecc mode of the device 3.17.2 invalid block replacement operation * start set block address = 0 check increment block address last block ? end no yes yes create (or update) no invalid block(s) table "ffffh" ? check "ffffh" at the 1st wo rd of sector 0 of spare area in 1st and 2nd page
onenand2g(kfg2g16q2m-debx) flash memory 138 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) referring to the diagram for further illustration, when an error happens in the nth page of block 'a' during program operation, copy the data in the 1st ~ (n-1)th page to the same location of block 'b' via data buffer0. then copy the nth page data of block 'a' in the data buffer1 to the nth page of block 'b' or any free block. do not further era se or program block 'a' but instead complete the operation by creating an 'invalid block table' or other appropriate scheme. block replacement operation sequence data buffer1 of the device 1st block a block b (n-1)th nth (page) ^ a 1st (n-1)th nth (page) ^ a an error occurs. 1 2 data buffer0 of the device 1 (assuming the nth page data is maintained)
onenand2g(kfg2g16q2m-debx) flash memory 139 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 4.1 absolute maximum ratings notes : 1. minimum dc voltage is -0.5v on input/ output pins. during transitions, this level should not fall to por level(typ. 1.5v@1.8 v device). maximum dc voltage may overshoot to vcc+2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended perio ds may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss vcc vcc -0.5 to + 2.45 v all pins v in -0.5 to + 2.45 temperature under bias extended t bias -30 to +125 q c industrial -40 to +125 storage temperature t stg -65 to +150 q c short circuit output current i os 5ma recommended operating temperature t a (extended temp.) -30 to +85 q c t a (industrial temp.) -40 to +85 4.2 operating conditions voltage reference to gnd notes : 1. vcc-core (or vcc) should reach the operating voltage level prior to or at the same time as vcc-io (or vccq). parameter symbol kfg2g16q2m unit min typ. max supply voltage v cc- core / vcc 1.7 1.8 1.95 v v cc- io / vccq v ss 000v 4.0 dc characteristics
onenand2g(kfg2g16q2m-debx) flash memory 140 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) note 1. ce should be vih for rdy. iobe should be 0 for int. note 2. i cc active for host access note 3. i cc active for internal operation. (without host access) note 4. vccq is e quivalent to vcc-io parameter symbol test conditions rms value unit min typ max input leakage current i li v in =v ss to v cc , v cc =v ccmax single - 1.0 - + 1.0 p a ddp - 2.0 - + 2.0 output leakage current i lo v out =v ss to v cc , v cc =v ccmax , ce or oe =v ih (note 1) single - 1.0 - + 1.0 p a ddp - 2.0 + 2.0 active asynchronous read current (note 2) i cc1 ce =v il , oe =v ih -815ma active burst read current (note 2) i cc2r ce =v il , oe =v ih ,we =v ih 66mhz - 20 30 ma 83mhz - 25 35 ma 1mhz - 3 4 ma 66mhz (ddp) -3038ma 83mhz (ddp) -3545ma 1mhz (ddp) -34ma active burst write current (note 2) i cc2w ce =v il , oe =v ih, we =v il 66mhz - 20 30 ma 83mhz - 25 35 ma 1mhz - 3 4 ma 66mhz (ddp) -3038ma 83mhz (ddp) -3545ma 1mhz (ddp) -34ma active asynchronous write current (note 2) i cc3 ce =v il , oe =v ih single -815ma ddp -1725ma active load current (note 3) i cc4 ce =v il , oe =v ih , we =v ih -3040ma active program current (note 3) i cc5 ce =v il , oe =v ih , we =v ih -2530ma active erase current (note 3) i cc6 ce =v il , oe =v ih , we =v ih -2025ma multi block erase current (note 3) i cc7 ce =v il , oe =v ih , we =v ih , 64blocks - 20 25 ma standby current i sb ce = rp =v cc r 0.2v single -1050 p a ddp - 20 100 input low voltage v il - -0.5 - 0.4 v input high voltage (note 4) v ih -v ccq -0.4 - v ccq +0.4 v output low voltage v ol i ol = 100 p a ,v cc =v ccmin , v ccq =v ccqmin --0.2v output high voltage v oh i oh = -100 p a , v cc =v ccmin , v ccq =v ccqmin v ccq -0.1 - - v 4.3 dc characteristics
onenand2g(kfg2g16q2m-debx) flash memory 141 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 5.1 ac test conditions parameter value (66mhz) value (83mhz) input pulse levels 0v to v cc 0v to v cc input rise and fall times clk 3ns 2ns other inputs 5ns 2ns input and output timing levels v cc /2 v cc /2 output load c l = 30pf c l = 30pf 0v v cc v cc /2 v cc /2 input pulse and test point input & output test point output load device under te s t * c l = 30pf including scope and jig capacitance 5.2 device capacitance notes: 1. the device may include invalid blocks when first shipped. additional invalid blocks may develop while being used. the number of valid blo cks is pre- sented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bits . do not erase or program factory-marked bad blocks. 2. the 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block. parameter symbol min typ. max unit valid block number single n vb 2008 - 2048 blocks ddp 4016 - 4096 blocks qdp 8032 - 8192 blocks capacitance (t a = 25 q c, v cc = 1.8v, f = 1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition single ddp qdp unit min max min max min max input capacitance c in1 v in =0v -10-20-40 pf control pin capacitance c in2 v in =0v -10-20-40 pf output capacitance c out v out =0v -10-20-40 pf int capacitance c int v out =0v -10-20-40 pf 5.3 valid block characteristics 5.0 ac characteristics
onenand2g(kfg2g16q2m-debx) flash memory 142 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) note 1. if oe is disabled at the same time or before ce is disabled, the output will go to high-z by t oez . if ce is disabled at the same time or before oe is disabled, the output will go to high-z by t cez . if ce and oe are disabled at the same time, the output will go to high-z by t oez . 2. it is the following clock of address fetch clock. parameter symbol 66mhz 83mhz unit min max min max clock clk 1 66 1 83 mhz clock cycle t clk 15 - 12 - ns initial access time t iaa -70-70ns burst access time valid clock to output delay t ba -11- 9ns avd setup time to clk t avds 5-4-ns avd hold time from clk t avdh 2-2-ns address setup time to clk t acs 5-4-ns address hold time from clk t ach 6-6-ns data hold time from next clock cycle t bdh 2.5 - 2 - ns output enable to data t oe -20-20ns ce disable to output & rdy high z t cez 1) -20-20ns oe disable to output high z t oez 1) -15-15ns ce setup time to clk t ces 6-4.5-ns clk high or low time t clkh/l t clk /3 - 5 - ns clk 2) to rdy valid t rdyo -11- 9ns clk to rdy setup time t rdya -11- 9ns rdy setup time to clk t rdys 4-3-ns ce low to rdy valid t cer -15-15ns 5.4 ac characteristics for synchronous burst read see timing diagrams 6.1, 6.2 and 6.3.
onenand2g(kfg2g16q2m-debx) flash memory 143 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) note: 1. if oe is disabled at the same time or before ce is disabled, the output will go to high-z by t oez . if ce is disabled at the same time or before oe is disabled, the output will go to high-z by t cez . if ce and oe are disabled at the same time, the output will go to high-z by t oez . these parameters are not 100% tested. parameter symbol kfg2g16q2m/ KFH4G16Q2M/ kfw8g16q2m unit min max access time from ce low t ce -76ns asynchronous access time from avd low t aa -76ns asynchronous access time from address valid t acc -76ns read cycle time t rc 76 - ns avd low time t avdp 12 - ns address setup to rising edge of avd t aavds 7-ns address hold from rising edge of avd t aavdh 6-ns output enable to output valid t oe -20ns ce disable to output & rdy high z 1) t cez -20ns oe disable to output high z 1) t oez -15ns ce low to rdy valid t cer -15ns we disable to avd enable t wea 15 - ns 5.6 ac characteristics for warm reset (rp ), hot reset and nand flash corereset see timing diagrams 6.19, 6.20 and 6.21. 5.5 ac characteristics for asynchronous read see timing diagrams 6.5, 6.6, 6.7 and 6.8. note: 1. these parameters are tested based on int bit of interrupt register. because the time on int pin is related to the pull-up an d pull-down resistor value. 2. the device may reset if trp < trp min(200ns), but this is not guaranteed. parameter symbol min max unit rp & reset command latch to bootram access tready1 (bootram) -5 p s rp & reset command latch(during load routines) to int high (note1) tready2 (nand flash array) -10 p s rp & reset command latch(during program routines) to int high (note1) tready2 (nand flash array) -20 p s rp & reset command latch(during erase routines) to int high (note1) tready2 (nand flash array) - 500 p s rp & reset command latch(not during internal routines) to int high (note1) tready2 (nand flash array) -10 p s rp pulse width (note2) trp 200 - ns
onenand2g(kfg2g16q2m-debx) flash memory 144 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 5.7 ac characteristics for asynchronous write see timing diagrams 6.9. parameter symbol min max unit we cycle time t wc 70 - ns avd low pulse width t avdp 12 - ns address setup time t awes 0 - ns address hold time t ah 30 - ns data setup time t ds 25 - ns data hold time t dh 0 - ns ce setup time t cs 0 - ns ce hold time t ch 10 - ns we pulse width t wpl 40 - ns we pulse width high t wph 30 - ns we disable to avd enable t wea 15 - ns ce disable to output & rdy high z t cez -20ns note : 1. target clock frequency is 83mhz parameter symbol 66mhz 83mhz unit min max min max clock clk 1) 166183mhz clock cycle t clk 15 - 12 - ns avd setup to clk t avds 5-4-ns avd hold time from clk t avdh 2-2-ns address setup time to clk t acs 5-4-ns address hold time from clk t ach 6-6-ns data setup time to clk t wds 5-4-ns data hold time from clk t wdh 2-2-ns we setup time to clk t wes 5-4-ns we hold time from clk t weh 6-6-ns clk high or low time t clkh/l t clk /3 - 5 - ns ce high pulse width t cehp 10 - 10 - ns clk to rdy valid t rdyo -11- 9ns clk to rdy setup time t rdya -11- 9ns rdy setup time to clk t rdys 4 - 3 -ns ce low to rdy valid t cer - 15 - 15 ns clock to ce disable t ceh 6-6-ns ce setup time to clk t ces 6 - 4.5 - ns ce disable to output & rdy high z t cez - 20 - 20 ns 5.8 ac characteristics for burst write operation see timing diagrams 6.10 and 6.11.
onenand2g(kfg2g16q2m-debx) flash memory 145 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) these parameters are tested based on int bit of interrupt register. because the time on int pin is related to the pull-up and p ull-down resistor value. parameter symbol min typ max unit sector load time(note 1) t rd1 -2335 p s page load time(note 1) t rd2 -3045 p s sector program time(note 1) t pgm1 - 205 720 p s page program time(note 1) t pgm2 - 220 750 p s otp access time(note 1) t otp - 500 700 ns lock/unlock/lock-tight/all block unlock time(note 1) t lock - 500 700 ns erase suspend time(note 1) t esp - 400 500 p s erase resume time(note 1) 1 block t ers1 -23ms 2~64 blocks t ers2 46ms number of partial program cycles in the page (including main and spare area) nop - - 4 cycles block erase time (note 1) 1 block t bers1 -23ms 2~64 blocks t bers2 -46ms multi block erase verify read time(note 1) t rd3 - 70 100 p s 5.9 ac characteristics for load/program/erase performance see timing diagrams 6.12, 6.13, and 6.17 5.10 ac characteristics for int auto mode see timing diagrams 6.23 parameter symbol min max unit command input to int low t wb -200ns 5.11 ac characteristics for synchronous burst block read see timing diagrams 6.4 parameter symbol typ. max unit int low period during synch burst block read t intl 1-us
onenand2g(kfg2g16q2m-debx) flash memory 146 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 6.1 8-word linear burst read mode with wrap around see ac characteristics table 5.4 6.2 continuous linear burst read mode with wrap around see ac characteristics table 5.4 6.0 timing diagrams t ces t avds t avdh t acs t ach t iaa t ba t bdh t clk ce clk avd oe dq0-dq15 a0-a15 | | | | | | | d6 d7 d0 d1 d2 d3 d7 t rdya t oe brwl=4 t cez t oez d0 t clkh t clkl t rdyo t cer hi-z rdy | t rdys hi-z 0 -1 1 2 3 4 t ces t avds t avdh t acs t ach t iaa t ba t bdh t clk hi-z ce clk avd oe dq0-dq15 rdy a0-a15 | | | | | | | | t rdys da da+1 da+2 da+3 da+4 da+5 da+n t rdya t oe brwl=4 t cez t oez da+n+1 hi-z t rdyo t cer 0 -1 1 2 3 4
onenand2g(kfg2g16q2m-debx) flash memory 147 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 6.3 synchronous burst block read operation timing see ac characteristics table 5.4 and 5.7. we ce clk t ds t wpl t cs t wph t wc fpa fba oe int t ch t cs avd v il t dh t rd2 sbbrcd fpc dq0-dq15 hi-z d0 d1 d2 rdy notes: asynchronous write was used in this timing diagram. synchronous write is also possible. 1. aa = address of address register ca = address of command register sbbrcd = synchronous burst block read command fba = flash block address fpa = flash page address ggg bsa = bufferram sector address fpc= number of flash page to be read (3pages ~ 64pages) . . . . . . . . . . . . . . . . . . . . . . . . aa aa a0-a15 t aavdh t aavds ca . . . start add aa aa bsa
onenand2g(kfg2g16q2m-debx) flash memory 148 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 6.4 synchronous burst block read timing see ac characteristics table 5.11 start page address setting number of pages synchronous burst block read command a0~ clk rdy high-z high-z int: indicator for datarams status (ready=high, busy=low) rdy: indicator for latency of sync burst block read burst length: 4, 8, 16, 32, 1k word, and continuous synchronous burst block read are available. a1~a4: for the fixed number of words linear burst block read, a1~a4 are start address of the each dataram. for detailed timing diagram, refer to chapter 6.3 we must be set high throughout the operation. a15 a1 a2 a3 a4 int . . . . . . . . . . .. . . . . . . . . . . . we oe avd high . . . . . . high . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . . . . . . . . . .. . . . 1st page out 2nd page out 3rd page out 4th page out dq0~ dq15 high-z . . . . . . . . . . .. . . . . . ce . . high . . . . . . . . .. . . . case 1 : bl=1k word synchronous burst block read t intl
onenand2g(kfg2g16q2m-debx) flash memory 149 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 1st burst data nth burst data start page address setting number of pages synchronous burst block read command ce clk rdy high-z nt bit : indicator for datarams status (ready=1, busy=0) rdy: indicator for latency of sync burst block read burst length: 4, 8, 16, 32, 1k word synchronous burst block read are available. a1-1 ~ a1-n: address where each burst data initiates, and this may differ for different settings of bsa and bl. n can be calculated by 1024w / bl. therefore, for above case, bsa=0200h and bl=8word. so that n=128, a1-1=0200h, a1-2=0208h ... a1-128=05f8h. we must be set high throughout the operation. f241h a1-1 a1-n int bit . . . .. . . . . . . . . . . . . . we oe avd high high . . . . . . . . .. . . . . .. . . . . .. . . . . .. . . . . .. . . dq[15] polling f241h dq[15] polling | | | | | | | | f241h dq[15] polling . high-z high case 2 : host reads int bit for ready/busy state indicator . . . .. . . . a0~ a15 dq0~ dq15 . . | |
onenand2g(kfg2g16q2m-debx) flash memory 150 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 6.6 asynchronous read (va transition after avd low) see ac characteristics table 5.5 6.5 asynchronous read (va transition before avd low) see ac characteristics table 5.5 note: va=valid read address, rd=read data. t oe va valid rd t ce t oez ce oe we a0-a15 clk v il avd hi-z hi-z rdy t avdp t aavdh dq0-dq15 t cez note: va=valid read address, rd=read data. t oe va valid rd t oez ce oe we a0-a15 clk v il avd t aa hi-z hi-z rdy t avdp t aavdh dq0-dq15 t wea t cez
onenand2g(kfg2g16q2m-debx) flash memory 151 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 6.8 asynchronous read (avd is tied to ce ) see ac characteristics table 5.5 note: va=valid read address, rd=read data. t oe va valid rd t oez ce oe we a0-a15 t acc clk v il avd t aavds hi-z hi-z rdy t avdp t aavdh dq0-dq15 t wea t cez note: va=valid read address, rd=read data. t oe va valid rd t ce t oez ce oe we a0-a15 t acc clk v il hi-z hi-z rdy t rc dq0-dq15 t cez 6.7 asynchronous read (va and avd transition after ce low) see ac characteristics table 5.5
onenand2g(kfg2g16q2m-debx) flash memory 152 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 6.9 asynchronous write see ac characteristics table 5.7 note: va=valid read address, wd=write data. ce we oe rp a0-a15 t cs dq0- valid wd t ds rdy va valid wd t wpl t wph t wc t dh t awes va t ah hi-z hi-z clk v il t ch t cs dq15
onenand2g(kfg2g16q2m-debx) flash memory 153 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 6.10 8-word linear burst write mode see ac characteristics table 5.8 t ces t avds t avdh t acs t ach t rdyo t wdh t wds t clk hi-z ce clk avd oe rdy | | | | | t rdys t rdya a0~ a15 t cer t clkh t clkl hi-z t cer | we t wes t weh t ceh -101234 brwl = 4 | dq0~ dq15 d0 d1 d2 d3 d4 d5 d7 t cez
onenand2g(kfg2g16q2m-debx) flash memory 154 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) t ces t avds t avdh t acs t ach t rdyo t wdh t wds t clk hi-z ce clk avd oe rdy t rdys t rdya t cer t clkh t clkl t cer we t wes t weh t ceh -1 0 1 2 3 4 brwl = 4 t cez t cehp brwl = 4 a0~ a15 dq0~ dq15 d0 d0 6.11 start initial burst write operation see ac characteristics table 5.8
onenand2g(kfg2g16q2m-debx) flash memory 155 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) notes: 1. aa = address of address register ca = address of command register lcd = load command lma = address of memory to be loaded ba = address of bufferram to load the data bd = program data sa = address of status register 2. in progress and complete refer to status register 3. status reads in this figure is asynchronous read, but status read in synchronous mode is also supported. load command sequence a0:a15 we ce clk t ds t dh t ch t wpl t cs t wph t wc ca ba ba lcd lma aa dq0-dq15 oe read data v il | | | | | | da da+1 t ah t awes int t ch t cs 6.12 load operation timing see ac characteristics tables 5.7 and 5.9 t rd1 or trd2
onenand2g(kfg2g16q2m-debx) flash memory 156 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 6.13 program operation timing see ac characteristics tables 5.7 and 5.9 notes: 1. aa = address of address register ca = address of command register pcd = program command pma = address of memory to be programmed ba = address of bufferram to load the data bd = program data sa = address of status register 2. in progress and complete refer to status register 3. status reads in this figure is asynchronous read, but status read in synchronous mode is also supported. program command sequence (last two cycles) a0:a15 we ce clk t ds t dh t ch t wpl t cs t wph t wc sa sa in progress complete aa dq0-dq15 oe read status data v il | | | | | | ba ca pcd pma bd t ah t awes int t ch t ch t cs t cs t pgm1 or tpgm2
onenand2g(kfg2g16q2m-debx) flash memory 157 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 1st data input address setting a0: a1 : address of dataram to be written. int: indicator for datarams status (ready=high, busy=low) ongoing status : indicated by ongo bit in controller status register [15] (f240h) 4kb data input : asynch write / synch write available. command input and int pin behavior is based on int auto mode. in int manual mode, writing 0 to interrupt register is required before command issue. a15 a1 int . .. . 4kb data into 2 datarams 2x program command ongoing status controller status register check plane1 / plane2 current : pass=0, fail=1 plane1 / plane2 previous: invalid (fixed to 0) dq0~ dq15 6.14 2x program operation timing
onenand2g(kfg2g16q2m-debx) flash memory 158 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 2x cache program command a1, a2, a3 : address of dataram to be written. int: indicator for datarams status (ready=high, busy=low) ongoing status : indicated by ongo bit in controller status register [15] (f240h) 4kb data input : asynch write / synch write available. command input and int pin behavior is based on int auto mode. in int manual mode, writing 0 to interrupt register is required before command issue. int . . 2x cache program command 2x program command ongoing status controller status register check plane1 / plane2 current : invalid (fixed to 0) plane1 / plane2 previous: invalid (fixed to 0) controller status register check plane1 / plane2 current : invalid plane1 / plane2 previous: pass=0, fail=1 controller status register check plane1 / plane2 current : pass=0, fail=1 plane1 / plane2 previous: pass=0, fail=1 1st data input 2nd data input address setting a0~ a15 a1 a2 high-z . .. . . . 4kb data into 2 datarams 4kb data into 2 datarams 3nd data input a3 4kb data into 2 datarams . .. . . . .. .. dq0~ dq15 6.15 2x cache program operation timing
onenand2g(kfg2g16q2m-debx) flash memory 159 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 1st data input 2nd data input 2x cache program command dq0~ a1, a2, a3 : address of dataram to be written. int: indicator for datarams status (ready=high, busy=low) ongoing status : indicated by ongo bit in controller status register [15] (f240h) 4kb data input : asynch write / synch write available. command input and int bit or pin behavior is based on int auto mode. note 1) int pin might toggle when int bit of chip1 turns to ready before host issues 2x program command on chip2. dq15 high-z int bit . .. . . . 4kb data into 2 datarams 2x cache program command 2x program command last data input . .. ongoing status controller status register check plane1 / plane2 current : invalid plane1 / plane2 previous: pass=0, fail=1 controller status register check plane1 / plane2 current : pass=0, fail=1 plane1 / plane2 previous: pass=0, fail=1 . .. 2x cache program command 2x cache program command 2x program command ongoing status controller status register check plane1 / plane2 current : invalid plane1 / plane2 previous: pass=0, fail=1 controller status register check plane1 / plane2 current : pass=0, fail=1 plane1 / plane2 previous: pass=0, fail=1 . .. chip1 chip2 . .. .. . .. .. controller status register check plane1 / plane2 current : invalid (fixed to 0) plane1 / plane2 previous: invalid (fixed to 0) controller status register check plane1 / plane2 current : invalid (fixed to 0) plane1 / plane2 previous: invalid (fixed to 0) int bit int pin . .. 1) ^ ^ 6.16 2x interleave cache program operation timing address setting a0~ a15 a1 a2 high-z . .. . . . an . .. 4kb data into 2 datarams 4kb data into 2 datarams 1st data input 2nd data input dq0~ dq15 high-z . . . . 4kb data into 2 datarams last data input . .. address setting a0~ a15 a1 a2 high-z . . an . .. 4kb data into 2 datarams 4kb data into 2 datarams . . . . . . . . . . . . . .
onenand2g(kfg2g16q2m-debx) flash memory 160 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 6.17 block erase operation timing see ac characteristics tables 5.7 and 5.9 notes: 1. aa = address of address register ca = address of command register ecd = erase command ema = address of memory to be erased sa = address of status register 2. in progress and complete refer to status register 3. status reads in this figure is asynchronous read, but status read in synchronous mode is also supported. erase command sequence (last two cycles) a0:a15 we ce t ds t dh t ch ca sa sa in progress complete ecd ema aa dq0-dq15 oe read status data t wpl t cs t wph t wc clk v il | | | | | | t ah t awes int t ch t cs t bers1
onenand2g(kfg2g16q2m-debx) flash memory 161 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) note: 1) bootcode copy operation starts after 400us from the moment that vcc reaches 1.7v. 2) 1k bytes bootcode copy takes 70us(estimated) from sector0 and sector1/page0/block0 of nand flash array to bootram. host can read bootcode in bootram(1k bytes) after bootcode copy completion. 3) int register goes low to high on the condition of bootcode-copy done and rp rising edge. if rp goes low to high before bootcode-copy done, int register goes to low to high as soon as bootcode-copy done system power sleep bootcode copy idle bootcode - copy done vcc =1.7v 3) 2) rp int onenand operation 0 (default) 1 iobe bit 1 (default) intpol bit high-z 1) int bit 0 (default) 1 6.18 cold reset timing
onenand2g(kfg2g16q2m-debx) flash memory 162 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 6.19 warm reset timing ce , oe rp t rp t ready1 rdy int high-z high-z t ready2 idle 1) operation status reset ongoing 2) bootram access 3) idle 1) int bit polling 4) notes: 1. the status which can accept any register based operation(load, program, erase command, etc). 2. the status where reset is ongoing. 3. the status allows only bootram(bl1) read operation for boot sequence.(refer to 7.2.2 boot sequence) 4. to read bl2 of boot sequence, host should wait int until becomes ready. and then, host can issue load command. (refer to 7.2.2 boot sequence, 7.1 methods of determing interrupt status) bit see ac characteristics table 5.6
onenand2g(kfg2g16q2m-debx) flash memory 163 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 6.20 hot reset timing note: 1. internal reset operation means that the device initializes internal registers and makes output signals go to default status and bufferram data are kept unchanged after warm/hot reset operations. 2. reset command : command based reset or register based reset 3. bp(boot partition): bootram area [0000h~01ffh, 8000h~800fh] 4. 00f0h for bp, and 00f3h for f220h avd bp(note 3) int a0~a15 we ce or f220h rdy operation or idle onenand reset idle onenand operation high-z dq0~dq15 00f0h or 00f3h 4) oe t ready 2 bit see ac characteristics table 5.6
onenand2g(kfg2g16q2m-debx) flash memory 164 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 6.22 data protection timing during power down 6.21 nand flash core reset timing avd ce f220h rdy operation or idle nand flash core reset idle onenand operation high-z 00f0h a0~a15 dq0~dq15 int we oe t ready 2 bit see ac characteristics table 5.6 v cc rp onenand logic reset & nand array write protected int onenand operation typ. 1.5v 0v the device is designed to offer protection from any involuntary program/erase during power-transitions. rp pin provides hardware protection and must be kept at v il before vcc drops to 1.5v
onenand2g(kfg2g16q2m-debx) flash memory 165 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) write command into command register int will automatically turn to busy state int will automatically turn back to ready state when designated operation is completed. note) int pin polarity is based on iobe=1 and int pol=1 (default) setting int pin int bit 6.23 int auto mode twb we dq cmd . . . . . . . . . . . . . see ac characteristics table 5.10
onenand2g(kfg2g16q2m-debx) flash memory 166 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) from time-to-time supplemental technical information and application notes pertaining to the design and operation of the device in a system are included in this section. contact your samsung representative to determine if additional notes are available. 7.1 methods of determining interrupt status there are two methods of determining interrupt status on the onenand. using the int pin or monitoring the interrupt status regi s- ter bit. the onenand int pin is an output pin function used to notify the host when a command has been completed. in cache read, synchronous burst block read and 2x cache program cases, int pin notifies that only trasferring from dataram to page buffer is completed. this provides a hardware method of signaling the completion of a program, erase, or load operation. in its normal state, the int pin is high if the int polarity bit is default. in case of normal int mode, before a command is w ritten to the command register, the int bit must be written to '0' so the int pin transitions to a low state indicating start of the operatio n. in case of int auto mode, int bit is written to 0 automatically right after command issued. upon completion of the command operation b y the onenands internal controller, int returns to a high state. int pin is a dq-type output except reset and 2x program in ddp allowing two int outputs to be or-tied together. in case of reset and 2x program in ddp, int pin operates as an open drain with 50k ohm. int does not float to a hi-z condition when ce is disabled or oe is disabled. refer to section 2.8 for additional information about int. int can be implemented by tying int to a host gpio or by continuous polling of the interrupt status register. int type (mono) int type (ddp) general operation dq type dq type reset operation (cold,warm,hot and flash core reset) and 2x program dq type open drain (with 50kohm) 7.0 technical and application notes
onenand2g(kfg2g16q2m-debx) flash memory 167 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) synchronous mode using the int pin when operating synchronously, int is tied directly to a host gpio. rdy could be conneceted as one of following guides. host onenand asynchronous mode using the int pin when configured to operate in an asynchronous mode, ce and avd of the onenand are tied to ce of the host. clk is tied to the host vss (ground). rdy is not connected. oe of the onenand and host are tied together and int is tied to a gpio. rdy(wait) oe clk ce rdy oe clk ce avd gpio int host onenand oe vss ce rdy oe clk ce avd gpio int host onenand oe clk ce rdy oe clk ce avd gpio int handshaking mode non-handshaking mode 7.1.1 the int pin to a host general purpose i/o int can be tied to a host gpio to detect the rising edge of int, signaling the end of a command operation. this can be configured to operate either synchronously or asynchronously as shown in the diagrams below. int command
onenand2g(kfg2g16q2m-debx) flash memory 168 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) synchronous mode using interrupt status register bit polling when operating synchronously, ce and avd of the onenand are tied to ce of the host, clk, oe , and dq pins on the host and onenand are tied together. rdy could be connected as one of following guides. asynchronous mode using interrupt status register bit polling when configured to operate in an asynchronous mode, ce and avd of the onenand are tied to ce of the host. clk is tied to the host vss (ground). rdy is not connected. oe and dq of the onenand and host are tied together. host onenand n.c oe ce rdy oe clk ce avd dq dq vss an alternate method of determining the end of an operation is to continuously monitor the interrupt status register bit instead of using the int pin. when using interrupt register instead of int pin, int must be unconnected. this can be configured in either a synchronous mode or an asynchronous mode. int command 7.1.2 polling the interrupt register status bit host onenand rdy(wait) oe clk ce rdy oe clk ce avd dq dq host onenand oe clk ce rdy oe clk ce avd dq dq handshaking mode non-handshaking mode
onenand2g(kfg2g16q2m-debx) flash memory 169 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) for general operation, int operates as normal output pin, so that tf is equivalent to tr (below 10ns). but since int operates a s open drain with 50k ohm for reset (cold/hot/warm/nand flash core) operations case and 2x program operation case at ddp option, the pull-up resistor value is related to tr(int). and appropriate value can be obtained with the following reference charts. 7.1.3 determining rp value (ddp, qdp only) busy state ready vcc voh tf tr vol vss ~50k ohm int vcc or vccq rp int pol = high (default) tr,tf ibusy [ma] rp(ohm) ibusy tr[us] KFH4G16Q2M @ vcc = 1.8v, ta = 25 q c , c l = 30pf 1k 10k 20k 30k 0.146 tf[ns] 1.126 2.192 2.912 5.98 5.74 5.73 5.72 1.76 0.18 0.09 40k 50k 3.485 3.952 5.72 5.72 0.045 0.06 0.036 open(100k) 5.416 0.000 a a a a a a
onenand2g(kfg2g16q2m-debx) flash memory 170 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) ~50k ohm int vcc or vccq rp int pol = low busy state ready voh tf tr vol vss vcc tr,tf ibusy [ma] rp(ohm) ibusy tf[us] KFH4G16Q2M @ vcc = 1.8v, ta = 25 q c , c l = 30pf 1k 10k 20k 30k 0.111 tr[ns] 0.959 1.669 2.218 7.53 6.73 6.71 6.74 1.76 0.18 0.09 40k 50k 2.655 3.012 6.81 6.92 0.045 0.06 0.036 open(100k) 4.129 0.000 a a a a a a
onenand2g(kfg2g16q2m-debx) flash memory 171 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) one of the best features onenand has is that it can be a booting device itself since it contains an internally built-in boot lo ader despite the fact that its core architecture is based on nand flash. thus, onenand does not make any additional booting device necessary for a system, which imposes extra cost or area overhead on the overall system. as the system power is turned on, the boot code originally stored in nand flash array is moved to bootram automatically and the n fetched by cpu through the same interface as srams or nor flashs if the size of the boot code is less than 1kb. if its size i s larger than 1kb and less than or equal to 3kb, only 1kb of it can be moved to bootram automatically and fetched by cpu, and the rest o f it can be loaded into one of the datarams whose size is 2kb by load command and cpu can take it from the dataram after finish- ing the code-fetching job for bootram. if its size is larger than 3kb, the 1kb portion of it can be moved to bootram automatica lly and fetched by cpu, and its remaining part can be moved to dram through two datarams using dual buffering and taken by cpu to reduce cpu fetch time. a typical boot scheme usually used to boot the system with onenand is explained at partition of nand flash array and onenand boot sequence. in this boot scheme, boot code is comprised of bl1, where bl stands for boot loader, bl2, and bl3. moreover, the size of the boot code is larger than 3kb (the 3rd case above). bl1 is called primary boot loader in other words. here is the ta ble of detailed explanations about the function of each boot loader in this specific boot scheme. boot loaders in onenand nand flash array of onenand is divided into the partitions as described at partition of nand flash array to show where each com - ponent of code is located and how much portion of the overall nand flash array each one occupies. in addition, the boot sequenc e is listed below and depicted at boot sequence. boot loader description bl1 moves bl2 from nand flash array to dram through two datarams using dual buffering bl2 moves os image (or bl3 optionally) from nand flash array to dram through two datarams using dual buffering bl3 (optional) moves or writes the image through usb interface 7.2.1 boot loaders in onenand boot sequence : 1. power is on bl1 is loaded into bootram 2. bl1 is executed in bootram bl2 is loaded into dram through two datarams using dual buffering by bl1 3. bl2 is executed in dram os image is loaded into dram through two datarams using dual buffering by bl2 4. os is running 7.2.2 boot sequence 7.2 boot sequence
onenand2g(kfg2g16q2m-debx) flash memory 172 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) reservoir file system os image nbl3 nbl2 nbl1 partition 6 block 162 block 2 block 1 block 0 partition 5 sector 0 sector 1 sector 2 sector 3 page 63 page 62 page 2 page 1 page 0 bl2 partition 4 partition 3 partition of nand flash array reservoir file system os image bl3 bl2 bl1 partition 6 block 162 block 2 block 1 block 0 partition 5 sector 0 sector 1 sector 2 sector 3 page 63 page 62 page 2 page 1 page 0 partition 4 partition 3 : : reservoir file system os image bl2 bl1 os image bl 2 nand flash array onenand dram onenand boot sequence bl1 internal bufferram data ram 1 data ram 0 boot ram(bl 1) note : step 2 and step 3 can be copied into dram through two datarams using dual buffering block 2047 step 1 step 2 step 3
onenand2g(kfg2g16q2m-debx) flash memory 173 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 0.10 max 0.45 0.05 0.32 0.05 0.9 0.10 bottom view top view a c e b d f 0.80x9=7.20 a 0.80x11=8.80 63- ? 0.45 0.05 g 4.40 0 . 8 0 b 0.20 m a b ? (datum a) (datum b) 2 543 1 6 3.60 #a1 index h 10.00 0.10 13.00 0.10 #a1 13.00 0.10 0 . 8 0 10.00 0.10 13.00 0.10 2g product (kfg2g16q2m) 4g product (KFH4G16Q2M) 0.10 max 0.45 0.05 0.32 0.05 1.1 0.10 bottom view top view a c e b d f 0.80x9=7.20 a 0.80x11=8.80 63- ? 0.45 0.05 g 4.40 0 . 8 0 b 0.20 m a b ? (datum a) (datum b) 2 543 1 6 3.60 #a1 index h 10.00 0.10 13.00 0.10 #a1 13.00 0.10 0 . 8 0 10.00 0.10 13.00 0.10 8.0 package dimensions
onenand2g(kfg2g16q2m-debx) flash memory 174 onenand4g(KFH4G16Q2M-debx) onenand8g(kfw8g16q2m-debx) 8g product (kfw8g16q2m) 0.10 max 0.45 0.05 0.32 0.05 1.3 0.10 bottom view top view a c e b d f 0.80x9=7.20 a 0.80x11=8.80 63- ? 0.45 0.05 g 4.40 0 . 8 0 b 0.20 m a b ? (datum a) (datum b) 2 543 1 6 3.60 #a1 index h 10.00 0.10 13.00 0.10 #a1 13.00 0.10 0 . 8 0 10.00 0.10 13.00 0.10

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